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X86 instruction listings

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The x86 instruction set refers to the set of instructions that x86-compatible microprocessors support. The instructions are usually part of an executable program, often stored as a computer file and executed on the processor.

Contents

The x86 instruction set has been extended several times, introducing wider registers and datatypes as well as new functionality.

x86 integer instructions

This is the full 8086/8088 instruction set. Most if not all of these instructions are available in 32-bit mode; they just operate on 32-bit registers (eax, ebx, etc.) and values instead of their 16-bit (ax, bx, etc.) counterparts. See also x86 assembly language for a quick tutorial for this processor family. The updated instruction set is also grouped according to architecture (i386, i486, i686) and more generally is referred to as x86_32 and x86_64 (also known as AMD64).

Added with Pentium MMX

Also MMX registers and MMX support instructions were added. They are usable for both integer and floating point operations, see below.

Added with AMD K6

AMD changed the CPUID detection bit for this feature from the K6-II on.

Added with ABM

LZCNT, POPCNT (POPulation CouNT) - advanced bit manipulation

Added with BMI1

ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT

Added with BMI2

BZHI, MULX, PDEP, PEXT, RORX, SARX, SHRX, SHLX

Added with TBM

BEXTR, BLCFILL, BLCI, BLCIC, BLCMASK, BLCS, BLSFILL, BLSIC, T1MSKC, TZMSK

Added with Pentium Pro

  • FCMOV variants: FCMOVB, FCMOVBE, FCMOVE, FCMOVNB, FCMOVNBE, FCMOVNE, FCMOVNU, FCMOVU
  • FCOMI variants: FCOMI, FCOMIP, FUCOMI, FUCOMIP

    • Added with SSE

    FXRSTOR, FXSAVE

    These are also supported on later Pentium IIs which do not contain SSE support

    Added with SSE3

    FISTTP (x87 to integer conversion with truncation regardless of status word)

    Undocumented x87 instructions

    FFREEP performs FFREE ST(i) and pop stack

    Added with Athlon

    Same as the SSE SIMD integer instructions which operated on MMX registers.

    EMMI instructions

    (added with 6x86MX from Cyrix, deprecated now)

    PAVEB, PADDSIW, PMAGW, PDISTIB, PSUBSIW, PMVZB, PMULHRW, PMVNZB, PMVLZB, PMVGEZB, PMULHRIW, PMACHRIW

    Added with K6-2

    FEMMS, PAVGUSB, PF2ID, PFACC, PFADD, PFCMPEQ, PFCMPGE, PFCMPGT, PFMAX, PFMIN, PFMUL, PFRCP, PFRCPIT1, PFRCPIT2, PFRSQIT1, PFRSQRT, PFSUB, PFSUBR, PI2FD, PMULHRW, PREFETCH, PREFETCHW

    Added with Athlon and K6-2+

    PF2IW, PFNACC, PFPNACC, PI2FW, PSWAPD

    Added with Geode GX

    PFRSQRTV, PFRCPV

    SSE instructions

    Added with Pentium III

    SSE SIMD floating-point instructions

    ADDPS, ADDSS, CMPPS, CMPSS, COMISS, CVTPI2PS, CVTPS2PI, CVTSI2SS, CVTSS2SI, CVTTPS2PI, CVTTSS2SI, DIVPS, DIVSS, LDMXCSR, MAXPS, MAXSS, MINPS, MINSS, MOVAPS, MOVHLPS, MOVHPS, MOVLHPS, MOVLPS, MOVMSKPS, MOVNTPS, MOVSS, MOVUPS, MULPS, MULSS, RCPPS, RCPSS, RSQRTPS, RSQRTSS, SHUFPS, SQRTPS, SQRTSS, STMXCSR, SUBPS, SUBSS, UCOMISS, UNPCKHPS, UNPCKLPS

    SSE SIMD integer instructions

    ANDNPS, ANDPS, ORPS, PAVGB, PAVGW, PEXTRW, PINSRW, PMAXSW, PMAXUB, PMINSW, PMINUB, PMOVMSKB, PMULHUW, PSADBW, PSHUFW, XORPS

    SSE2 instructions

    Added with Pentium 4

    SSE2 SIMD floating-point instructions

    SSE2 data movement instructions
    SSE2 packed arithmetic instructions
    SSE2 logical instructions
    SSE2 compare instructions
    SSE2 shuffle and unpack instructions
    SSE2 conversion instructions
  • CMPSD and MOVSD have the same name as the string instruction mnemonics CMPSD (CMPS) and MOVSD (MOVS); however, the former refer to scalar double-precision floating-points whereas the latters refer to doubleword strings.

    • SSE3 instructions

    Added with Pentium 4 supporting SSE3 Also see integer and floating-point instructions added with Pentium 4 SSE3

    SSE3 SIMD floating-point instructions

  • ADDSUBPD, ADDSUBPS (for Complex Arithmetic)
  • HADDPD, HADDPS, HSUBPD, HSUBPS (for Graphics)
  • MOVDDUP, MOVSHDUP, MOVSLDUP (for Complex Arithmetic)

    • SSE3 SIMD integer instructions

  • LDDQU (Instructionally equivalent to MOVDQU. For video encoding)

    • SSSE3 instructions

    Added with Xeon 5100 series and initial Core 2

  • PSIGNW, PSIGND, PSIGNB
  • PSHUFB
  • PMULHRSW, PMADDUBSW
  • PHSUBW, PHSUBSW, PHSUBD
  • PHADDW, PHADDSW, PHADDD
  • PALIGNR
  • PABSW, PABSD, PABSB

    • SSE4.1

    Added with Core 2 manufactured in 45nm

    SSE4.1 SIMD floating-point instructions

  • DPPS, DPPD
  • BLENDPS, BLENDPD, BLENDVPS, BLENDVPD
  • ROUNDPS, ROUNDSS, ROUNDPD, ROUNDSD
  • INSERTPS, EXTRACTPS

    • SSE4.1 SIMD integer instructions

  • MPSADBW
  • PHMINPOSUW
  • PMULLD, PMULDQ
  • PBLENDVB, PBLENDW
  • PMINSB, PMAXSB, PMINUW, PMAXUW, PMINUD, PMAXUD, PMINSD, PMAXSD
  • PINSRB, PINSRD/PINSRQ, PEXTRB, PEXTRW, PEXTRD/PEXTRQ
  • PMOVSXBW, PMOVZXBW, PMOVSXBD, PMOVZXBD, PMOVSXBQ, PMOVZXBQ, PMOVSXWD, PMOVZXWD, PMOVSXWQ, PMOVZXWQ, PMOVSXDQ, PMOVZXDQ
  • PTEST
  • PCMPEQQ
  • PACKUSDW
  • MOVNTDQA

    • SSE4a

    Added with Phenom processors

  • EXTRQ/INSERTQ
  • MOVNTSD/MOVNTSS

    • SSE4.2

    Added with Nehalem processors

  • CRC32
  • PCMPESTRI
  • PCMPESTRM
  • PCMPISTRI
  • PCMPISTRM
  • PCMPGTQ

    • Intel AES instructions

    6 new instructions.

    Intel SHA instructions

    7 new instructions.

    Undocumented instructions

    The x86 CPUs contain undocumented instructions which are implemented on the chips but not listed in some official documents. They can be found in various sources across the Internet, such as Ralf Brown's Interrupt List and at sandpile.org

    References

    X86 instruction listings Wikipedia
    (Text) CC BY-SA