Multiple patterning

Pitch Splitting

The earliest form of multiple patterning involved simply dividing a pattern into two or three parts, each of which may be processed conventionally, with the entire pattern combined at the end in the final layer. This is sometimes called pitch splitting, since two features separated by one pitch cannot be imaged, so only skipped features can be imaged at once. It is also named more directly as "LELE" (Litho-Etch-Litho-Etch). This approach has been used for the 20 nm and 14 nm nodes. The additional cost of extra exposures was tolerated since only a few critical layers would need them. A more serious concern was the effect of feature-to-feature positioning errors (overlay). Consequently, the self-aligned sidewall imaging approach (described below) has succeeded this approach.

A "brute force" approach for patterning trenches involves a sequence of (at least) two separate exposures and etchings of independent patterns into the same layer. For each exposure, a different photoresist coating is required. When the sequence is completed, the pattern is a composite of the previously etched subpatterns. By interleaving the subpatterns, the pattern density can theoretically be increased indefinitely, the half-pitch being inversely proportional to the number of subpatterns used. For example, a 25 nm half-pitch pattern can be generated from interleaving two 50 nm half-pitch patterns, three 75 nm half-pitch patterns, or four 100 nm half-pitch patterns. The feature size reduction will most likely require the assistance of techniques such as chemical shrinks, thermal reflow, or shrink assist films. This composite pattern can then be transferred down into the final layer.

A possible application would be, for example, dividing the contact layer into two separate groups: gate contacts and source/drain contacts, each defining its own mask. IMEC recently used an approach like this to demonstrate a 45 nm node 6-transistor SRAM cell using dry lithography [3].

This is best described by considering a process example. A first exposure of photoresist is transferred to an underlying hardmask layer. After the photoresist is removed following the hardmask pattern transfer, a second layer of photoresist is coated onto the sample and this layer undergoes a second exposure, imaging features in between the features patterned in the hardmask layer. The surface pattern is made up of photoresist features edged between mask features, which can be transferred into the final layer underneath. This allows a doubling of feature density. The Interuniversity Microelectronics Centre (IMEC, Belgium) recently used this approach to pattern the gate level for its 32 nm half-pitch demonstration.

A concern with the use of this approach is the discrepancy and delay between the second photoresist pattern and the first hardmask pattern, resulting in an additional source of variation.

A variation on this approach which eliminates the first hardmask etch is resist freezing,[4] which allows a second resist coating over the first developed resist layer. JSR has demonstrated 32 nm lines and spaces using this method,[5] where the freezing is accomplished by surface hardening of the first resist layer.

In recent years, the scope of the term 'pitch splitting' has gradually been expanded to include techniques involving sidewall spacers.

Sidewall Image Transfer

In spacer patterning, a spacer is a film layer formed on the sidewall of a pre-patterned feature. A spacer is formed by deposition or reaction of the film on the previous pattern, followed by etching to remove all the film material on the horizontal surfaces, leaving only the material on the sidewalls. By removing the original patterned feature, only the spacer is left. However, since there are two spacers for every line, the line density has now doubled. This is commonly referred to as Self-Aligned Doubled Patterning (SADP). The spacer technique is applicable for defining narrow gates at half the original lithographic pitch, for example.

As pitch splitting has become more difficult due to possible differences in feature positions between different exposed parts, sidewall image transfer (SIT) has become more recognized as the necessary approach. The SIT approach typically requires a spacer layer to be formed on an etched feature's sidewall. If this spacer corresponds to a conducting feature, then ultimately it must be cut at no less than two locations to separate the feature into two or more conducting lines as typically expected. On the other hand, if the spacer corresponds to a dielectric feature, cutting would not be necessary. The prediction of how many cuts would be needed for advanced logic patterns has been a large technical challenge. Many approaches for spacer patterning have been published (some listed below), all targeting the improved management (and reduction) of the cuts.

As spacer materials are commonly hardmask materials, their post-etch pattern quality tends to be superior compared to photoresist profiles after etch, which are generally plagued by line edge roughness.

The main issues with the spacer approach are whether the spacers can stay in place after the material to which they are attached is removed, whether the spacer profile is acceptable, and whether the underlying material is attacked by the etch removing the material attached to the spacer. Pattern transfer is complicated by the situation where removal of the material adjacent to the spacers also removes a little of the underlying material. This results in higher topography on one side of the spacer than the other. Any misalignment of masks or excursion in pre-patterned feature critical dimension (CD) will cause the pitch between features to alternate, a phenomenon known as pitch walking.

The positioning of the spacer also depends on the pattern to which the spacer is attached. If the pattern is too wide or too narrow, the spacer position is affected. However, this would not be a concern for critical memory feature fabrication processes which are self-aligned.

Self-aligned contact/via patterning

Self-aligned contact and via patterning is an established method for patterning multiple contacts or vias from a single lithographic feature. It makes use of the intersection of an enlarged feature resist mask and underlying trenches which are surrounded by a pre-patterned hardmask layer. This technique is used in DRAM cells and has been extended to patterning of active areas (more discussion below under "Industrial adoption"). It is also used for advanced logic to avoid multiple exposures of pitch-splitting contacts and vias.

Spacer-is-Dielectric (SID) SADP

In self-aligned double patterning (SADP), the number of cut/block masks may be reduced or even eliminated in dense patches when the spacer is used to directly pattern inter-metal dielectric instead of metal features. The reason is the cut/block locations in the core/mandrel features are already patterned in the first mask.

Other multi-patterning techniques

There have been numerous concerns that multiple patterning diminishes or even reverses the node-to-node cost reduction expected with Moore's Law. EUV is more expensive than three 193i exposures (i.e., LELELE), considering the throughput. Moreover, EUV is more liable to print smaller mask defects not resolvable by 193i.

Self-Aligned Triple Patterning (SATP)

Self-aligned triple patterning has been considered as a promising successor to SADP, due to its introduction of a second spacer offering additional 2D patterning flexibility and higher density. A total of two masks (mandrel and trim) is sufficient for this approach. The only added cost relative to SADP is that of depositing and etching the second spacer. The main disadvantage of SATP succeeding SADP is that it would only be usable for one node. For this reason, self-aligned quadruple patterning (SAQP) is more often considered.

Protrusion Spacer Cutting and Linking Features

Mandrel or spacer core patterns can be designed to cut their own spacer patterns. A pair of opposing line protrusions can effectively squeeze out any feature in between if a spacer with a thickness exceeding half the distance between the protrusions is deposited, followed by the feature deposition. This is ideal for use in SID SADP schemes. A similar approach is the use of linked features, i.e., narrow constrictions which separate features in spacer patterning without cutting.

The protrusion cutting technique helps reduce the amount of cutting that is needed, and also enables the grid routing method described by Toshiba. The number of masks used for SAQP is the same as for SADP (1 mandrel/core, 1 trim/cut/block), since only pitch-doubled patterns need cutting. The remaining patterns do not need cutting or trimming, since they are patterned through the same initial exposure.

A similar approach to protrusion cutting is the concept of the linking feature. The linking feature is a narrow constriction which separates features when the sidewall spacer is deposited and patterned. Line jogs, possibly track changing, are necessary to establish the linking feature.

Complementary polarity exposures

The method of complementary exposures proposed in 2012 is another way of reducing mask exposures for multiple patterning. Instead of multiple mask exposures for individual vias, cuts or blocks, two exposures of opposing or complementary polarity are used, so that one exposure removes portions of the previous exposure pattern.

Cut Selection Layer

The cut pattern may also be generated by spacer patterning with pattern trimming/cutting, rather than by direct exposure. The key benefit is that the cut pattern will not suffer from CD errors associated with the exposure process, such as dose error, focus error, etc. As one or two masks are required to cut a spacer loop, the total number of masks required would be 3 to 4:

EUV vs. Multiple Patterning

The cost of a single EUV mask exposure is more than 3x that of an immersion mask exposure, from the relative scanner throughput consideration (275 WPH vs. 85 WPH); the deposition and etch costs are relatively much lower. Higher doses to reduce shot noise would increase the cost of EUV dramatically. Other considerations, related to defect management, also bring up the cost of EUV mask exposure further.

Beyond 18 nm half-pitch, with no pellicle for EUV in its current state, a cost-reduced SATP or SAQP is expected to be put in place; SAQP is already in use for NAND flash. SAQP is also able to be used from 18 to 12 nm half-pitch, while EUV cannot address the 12 nm half-pitch.

At the 2016 EUVL Workshop, ASML reported that the 0.33 NA NXE EUV tools would not be capable of standard single exposure patterning for the 11-13 nm half-pitch expected at the 5 nm node. A higher NA of 0.55 would allow single exposure EUV patterning of fields which are half the 26 mm x 33 mm standard field size. However, some products, such as NVIDIA's Pascal Tesla P100, will be bisected by the half-field size, and therefore require stitching of two separate exposures. In any case, two half-field scans consume twice as much acceleration/deceleration overhead as a single full-field scan.

The existing 0.33 NA EUV tools are challenged below 16 nm half-pitch resolution. In addition, tip-to-tip gaps are already problematic for 16 nm dimensions. Hence more than a single EUV exposure would be needed at a minimum for the 7 nm and 5 nm nodes.

The use of EUV for cutting exposures is also problematic for feature sizes relevant to 7 nm node and below, as such features are also aggravated by the shot noise issue.

Directed Self-Assembly

The number of masks may be reduced with the use of directed self-assembly (DSA) due to the provision of gridded cuts all at once within a printed area, which can then be selected with a final exposure. Alternatively, the cut pattern itself may be generated as a DSA step.

Much progress had been reported on the use of PMMA-PS block copolymers to define sub-20 nm patterns by means of self-assembly, guided by surface topography (graphoepitaxy) and/or surface chemical patterning (chemoepitaxy). The key benefit is the relatively simple processing, compared to multiple exposures or multiple depositions and etching. The main drawback of this technique is the relatively limited range of feature sizes and duty cycles for a given process formulation. Typical applications have been regular lines and spaces as well as arrays of closely packed holes or cylinders. However, random, aperiodic patterns may also be generated using carefully defined guiding patterns.

The line edge roughness in block copolymer patterns is strongly dependent on the interface tension between the two phases, which in turn, depends on the Flory "chi" (χ) parameter. A higher value of χ is preferred for reduced roughness; the interfacial width between domains is equal to 2a(6χ)^−1/2, where a is the statistical polymer chain length. Moreover, χN > 10.5 is required for sufficient phase segregation, where N is the degree of polymerization (number of monomer repeats in the chain). On the other hand, the half-pitch is equal to 2(3/π²)^1/3aN^2/3χ^1/6. The fluctuations of the pattern widths are actually only weakly (square root) dependent on the logarithm of the half-pitch, so they become more significant relative to smaller half-pitches.

Merged hole separation by etch shrink

Tokyo Electron Ltd (TEL) was able to resolve two merged contact holes by applying an etch shrink. 31-32 nm contact half-pitch was achieved through this method.

2D SID Spacer Patterning

The use of SID may be applied to 2D arrays, by iteratively adding features equidistant from the previously present features, doubling the density with each iteration.

Triangular Spacer (Honeycomb Structure) Patterning

Samsung recently demonstrated DRAM patterning using a honeycomb structure (HCS) suitable for 20 nm and beyond. Each iteration of spacer patterning triples the density, effectively reducing 2D pitch by a factor of sqrt(3).

Industrial adoption

Memory patterns are already patterned by quadruple patterning for NAND and crossed quadruple/double patterning for DRAM. These patterning techniques are self-aligned and do not require custom cutting or trim masks. For 2x-nm DRAM and flash, double patterning techniques should be sufficient.

Current EUV throughput is still more than 3x slower than 193 nm immersion lithography, thus allowing the latter to be extended by multiple patterning. Furthermore, the lack of an EUV pellicle is also prohibitive.

As of 2016, Intel is using SADP for its 10 nm node. Intel is using triple patterning for some critical layers at its 14 nm node, which is the LELELE approach. Triple patterning is already demonstrated in 10 nm tapeout, and is already an integral part of Samsung's 10 nm process. TSMC is deploying 7 nm in 2017 with multiple patterning; specifically, pitch-splitting, down to 40 nm pitch. Beyond the 5 nm node, multiple patterning, even with EUV assistance, would be economically challenging, since the departure from EUV single exposure would drive up the cost even higher. However, at least down to 12 nm half-pitch, LELE followed by SADP (SID) appears to be a promising approach, using only two masks, and also using the most mature double patterning techniques, LELE and SADP.

Patterning Costs

Ref.: A. Raley et al., Proc. SPIE 9782, 97820F (2016).

Compared to 193i SADP, EUV SADP cost is dominated by the EUV tool exposure, while the 193i SAQP cost difference is from the added depositions and etches. The processing cost and yield loss at a lithographic tool is expected to be highest in the whole integrated process flow due to the need to move the wafer to specific locations at high speed. EUV further suffers from the shot noise limit, which forces the dose to increase going for successive nodes. On the other hand, depositions and etches process entire wafers at once, without the need for wafer stage motion in the process chamber. In fact, multiple layers may be added under the resist layer for anti-reflection or etch hard-mask purposes, just for conventional single exposure.

Multi-Patterning Options

Cutting lines to form irregular patterns uses the maximum number of masks. However, minimum pitch lines with dense cut locations contribute to higher capacitance by adding more locations and more area of minimum spacing. 2D patterning is generally preferred, but requires sufficient exposed feature pitch, followed by sufficient splitting or division of the pitch. On the other hand, LELE, LELELE, and SADP (SID) can avoid line cuts, while SATP or SAQP with grid routing can minimize line cuts. EUV 2D patterning is limited to >32 nm pitch. For 16-18 nm half-pitch, the horizontal-vertical bias is over 3 nm, close to a node difference. Consequently, EUV would require double patterning for its introduction at 7 nm node below 20 nm half-pitch; this may prove too costly to implement against the already established LELELE triple patterning, or the immersion-based combination of mature double patterning techniques LELE+SADP or the implementation of SAQP, which is twice applied SADP, especially the SID form of SADP, with LELE and SID SADP already established for 32 nm and 24 nm half-pitch, respectively.

Notes: LELE=Litho-(followed by)Etch 2 times; LELELE=Litho-(followed by)Etch 3 times; SADP=Self-Aligned (Spacer) Double Patterning; SID = Spacer-Is-Dielectric; SAQP=Self-Aligned Quadruple Patterning

From a lithographic quality point of view, pitch quartering with 193 nm immersion is better than EUV single exposure. For example, 18 nm half-pitch with 0.33 NA EUV has k1=0.44, while 4x18=72 nm half-pitch with 1.35 NA immersion gives k1=0.50. The ~14% advantage is always maintained across target pitch. The difficulty increases faster as k1 drops below 0.35. On the other hand, multiple passes would present another difficulty for quadruple patterning. Properly shaping the mandrel is not trivial. Long lines running in one direction require the most cuts; a cut exposure and mask is needed for every path turn. In contrast, spacer patterns with path turns already included do not require cutting if they are used for encapsulating metal.

As the number of masks for a given layer increases, the cost for patterning that layer also increases. It is especially severe when a layer previously requiring only one mask now requires two masks; in this case the cost may roughly be expected to be doubled. On the other hand, the reduced device area from the reduced pitch allows the cost per device to be reduced. The larger pitch reduction allows a larger reduction of cost per device, which counters the effect of increasing mask count.

Mask Costs

The mask cost strongly benefits from the use of multiple patterning. The EUV single exposure mask has smaller features which take much longer to write than the immersion mask. Even though mask features are 4x larger than wafer features, the number of shots is exponentially increased for much smaller features. Furthermore, the sub-100 nm features on the mask are also much harder to pattern, with absorber heights ~70 nm.

Wafer Productivity

Note: WPM = WPH * # tools * uptime / # passes * 24 hrs/day * 30 days/month. Normalized WPM = WPM/(WPM for EUV 1 pass)

Multiple patterning with immersion scanners can be expected to have higher wafer productivity than EUV, even with as many as 4 passes per layer, due to faster wafer exposure throughput (WPH), a larger number of tools being available, and higher uptime.

Multiple Patterning Specific Issues

Multiple patterning entails the use of many processing steps to form a patterned layer, where conventionally only one lithographic exposure, one deposition sequence and one etch sequence would be sufficient. Consequently, there are more sources of variations and possible yield loss in multiple patterning. Where more than one exposure is involved, e.g., LELE or cut exposures for SAQP, the alignment between the exposures must be sufficiently tight. Current overlay capabilities are ~0.6 nm for exposures of equal density (e.g., LELE) and ~2.0 nm for dense lines vs. cuts/vias (e.g., SADP or SAQP) on dedicated or matched tools. In addition, each exposure must still meet specified width targets. Where spacers are involved, the width of the spacer is dependent on the initial deposition as well as the subsequent etching duration. Where more than one spacer is involved, each spacer may introduce its own width variation.

Mainstream Use in NAND Flash

Multiple patterning is routinely used for NAND Flash memory manufacturing. 14 nm is the smallest dimension achieved in 2016. 3D NAND Flash also includes SADP.

Another cost perspective comes from comparing patterning with multiple spacers vs. 3D NAND Flash fabrication, which requires at least 64 distinct layer depositions and etches of those same layers. 16 nm planar NAND requires SAQP (2x SADP) and is the cheapest memory product offered in 2016.

10nm FinFETs

Samsung announced mass production of 10 nm FinFETs in October 2016, featuring triple patterning. Samsung also has developed self-aligned triple patterning (US Patent 9412604).

7nm and 5nm FinFETs

Self-aligned quadruple patterning is already the established process to be used for patterning fins for 7 nm and 5 nm FinFETs. With SAQP, each patterning step gives a critical dimension uniformity (CDU) value in the sub-nanometer range (3 sigma).