The Design Automation Standards Committee (DASC) is a subgroup of interested individuals members of the Institute of Electrical and Electronics Engineers (IEEE) Computer Society and Standards Association. It oversees IEEE Standards that are related to computer-aided design (known as design automation). It is part of the IEEE Computer Society.
This group sponsors and develops standards under the policies of the IEEE.
The group started in the summer of 1984 at the Design Automation Conference. Initially, the group supported VHDL as a standard, but extended its coverage to Verilog, and then additional areas in the design automation space.
After going through a period of very few meetings in 2004–06 which ended with some contention about Power standards (see Common Power Format and Unified Power Format), the group developed new and explicit policies and procedures. With these procedures approved in 2007, the group began meeting monthly via teleconference. Active meetings include EDA companies, System integration companies, Electronic Intellectual Property (IP developers, and Semiconductor companies, and individuals interested in these topics.
Beginning in 2007, the group began to award the Ron Waxman Design Automation Standards Committee Meritorious Service Award. This award was named after the early and consistently contributing organizer of the DASC, Ron Waxman.
The first recipient of the award in 2007 was Gabe Moretti.
The biggest center of interest in the DASC has been around language based design and verification standards stemming from the key hardware description language standards VHDL and Verilog. From these have flowed standards for timing, synthesis, math routines, test, power, encryption, and meta-data for the topics above.
The emphasis of the group has also grown to embrace standards being developed in analog-mixed signal and other extensions driven by these needs.
The active Working Groups are:VHDL Working Groups
P1076 Standard VHDL Language Reference Manual (VASG)
P1076.1 Standard VHDL Analog and Mixed-Signal Extensions (VHDL-AMS)
P1076.1.1 Standard VHDL Analog and Mixed-Signal Extensions - Packages for Multiple Energy Domain Support (StdPkgs) - this group is now part of 1076.1
SystemVerilog Working Groups
P1800 SystemVerilog: Unified Hardware Design, Specification and Verification Language (SV-IEEE1800) [cosponsored with IEEE-SA CAG]
P1647 Standard for the Functional Verification Language 'e' (eWG)
P1699 Rosetta System Level Design Language Standard (WG)
P1734 Standard for Electronic Design Intellectual Property (IP) Quality (WG)
P1801 Standard for the Design & Verification of Low Power ICs
The inactive Working Groups are:P1076.2 IEEE Standard VHDL Mathematical Packages (math)
P1076.3 Standard VHDL Synthesis Packages (vhdlsynth)
P1164 Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164) (vhdl-std-logic)
P1076.4 Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification (VITAL) - This group is now part of 1076.
VHDL-200x: the next revision
Issues Screening and Analysis Committee (ISAC)
VHDL Programming Language Interface Task Force (VHPI)
P1364 Standard for Verilog Hardware Description Language (IEEEVerilog)- this group is now part of P1800
P1364.1 Standard for Verilog Register Transfer Level Synthesis (VLOG-Synth)
P1481 Standard for Integrated Circuit (IC) Open Library Architecture (OLA) (IEEE1481R)
P1497 Standard for Standard Delay Format (SDF) for the Electronic Design Process (sdf)
P1499 Standard Interface for Hardware Description Models of Electronic Components (OMF)
P1577 Object Oriented VHDL (oovhdl)
P1603 Standard for an Advanced Library Format (ALF) Describing Integrated Circuit (IC) Technology, Cells, and Blocks (ALF)
P1604 Library IEEE (libieee)
P1076.6 Standard for VHDL Register Transfer Level (RTL) Synthesis (SIWG)
P1666 Standard System C Language Reference Manual (systemc) [cosponsored with IEEE-SA CAG]
P1685 SPIRIT XML Standard for IP Description (IEEE-1685)
P1735 Recommended Practice for Encryption and [Use Rights] Management of Electronic Design Intellectual Property (IP) (WG)
P1778 ESTEREL v7 Language Standardization (WG)
P1850 Standard for PSL: Property Specification Language (IEEE-1850)
A project is designated by its IEEE-assigned number prefixed with the letter "P".