The ARM Cortex-M family are ARM microprocessor cores which are designed for use in microcontrollers, ASICs, ASSPs, and SoC. Cortex-M cores are commonly used as dedicated microcontroller chips, but also are "hidden" inside of SoC chips as power management controllers, I/O controllers, system controllers, touch screen controllers, smart battery controllers, and sensors controllers.
Though 8-bit microcontrollers were very popular in the past, Cortex-M has slowly been chipping away at the 8-bit market as the prices of low-end Cortex-M chips have moved downward. Cortex-M have become a popular replacements for 8-bit chips in applications that benefit from 32-bit math operations, and replacing older legacy ARM cores such as ARM7 and ARM9.
ARM Holdings neither manufactures nor sells CPU devices based on its own designs, but rather licenses the processor architecture to interested parties. ARM offers a variety of licensing terms, varying in cost and deliverables. To all licensees, ARM provides an integratable hardware description of the ARM core, as well as complete software development toolset and the right to sell manufactured silicon containing the ARM CPU.
Integrated device manufacturers (IDM) receive the ARM Processor IP as synthesizable RTL (written in Verilog). In this form, they have the ability to perform architectural level optimizations and extensions. This allows the manufacturer to achieve custom design goals, such as higher clock speed, very low power consumption, instruction set extensions, optimizations for size, debug support, etc. To determine which components have been included in a particular ARM CPU chip, consult the manufacturer datasheet and related documentation.
Some of the most important options for the Cortex-M cores are:
SysTick timer: A 24-bit system timer that extends the functionality of both the processor and the Nested Vectored Interrupt Controller (NVIC). When present, it also provides an additional configurable priority SysTick interrupt. Though the SysTick timer is optional, it is very rare to find a Cortex-M microcontroller without it.
Bit-Band: Maps a complete word of memory onto a single bit in the bit-band region. For example, writing to an alias word will set or clear the corresponding bit in the bit-band region. This allows every individual bit in the bit-band region to be directly accessible from a word-aligned address, and individual bits to be toggled from C/C++ without performing a read-modify-write sequence of instructions. Though the bit-band is optional, it is less common to find a Cortex-M3 and Cortex-M4 microcontroller without it. Some Cortex-M0 and Cortex-M0+ microcontrollers have bit-band.
Memory Protection Unit (MPU): Provides support for protecting regions of memory through enforcing privilege and access rules. It supports up to eight different regions, each of which can be split into a further eight equal-size sub-regions.
Tightly-Coupled Memory (TCM): Low-latency RAM that is used to hold critical routines, data, stacks. It is typically the fastest memory in the microcontroller.
Note: Most Cortex-M3 and M4 chips have bit-band and MPU. The bit-band option can be added to the Cortex-M0 / M0+ using the Cortex-M System Design Kit.
Note: Software should validate the existence of a feature before attempting to use it.
Additional silicon options:
Data endianness: Little-endian or big-endian. Unlike legacy ARM cores, the Cortex-M is permanently fixed in silicon as one of these choices.
Interrupts: 1 to 32 (Cortex-M0/M0+/M1), 1 to 240 (Cortex-M3/M4/M7/M23), 1 to 480 (Cortex-M33).
Wake-up interrupt controller: Optional.
Vector Table Offset Register: Optional. Not available for Cortex-M0.
Instruction fetch width: 16-bit only, or mostly 32-bit.
User/privilege support: Optional.
Reset all registers: Optional.
Single-cycle I/O port: Optional. Available for Cortex-M0+/M23.
Debug Access Port (DAP): None, SWD, JTAG and SWD. (optional for all Cortex-M cores)
Halting debug support: Optional.
Number of watchpoint comparators: 0 to 2 (Cortex M0/M0+/M1), 0 to 4 (Cortex-M3/M4/M7/M23/M33).
Number of breakpoint comparators: 0 to 4 (Cortex M0/M0+/M1/M23), 0 to 8 (Cortex-M3/M4/M7/M33).
The Cortex-M0 / M0+ / M1 implement the ARMv6-M architecture, the Cortex-M3 implements the ARMv7-M architecture, and the Cortex-M4 / M7 implements the ARMv7E-M architecture. The architectures are binary instruction upward compatible from ARMv6-M to ARMv7-M to ARMv7E-M. Binary instructions available for the Cortex-M0 / M0+ / M1 can execute without modification on the Cortex-M3 / M4 / M7. Binary instructions available for the Cortex-M3 can execute without modification on the Cortex-M4 / M7 / M33. Only Thumb-1 and Thumb-2 instruction sets are supported in Cortex-M architectures, but the legacy 32-bit ARM instruction set isn't supported.
All six Cortex-M cores implement a common subset of instructions that consists of most Thumb-1, some Thumb-2, including a 32-bit result multiply. The Cortex-M0 / M0+ / M1 / M23 were designed to create the smallest silicon die, thus having the fewest instructions of the Cortex-M family.
The Cortex-M0 / M0+ / M1 include Thumb-1 instructions, except new instructions (CBZ, CBNZ, IT) which were added in ARMv7-M architecture. The Cortex-M0 / M0+ / M1 include a minor subset of Thumb-2 instructions (BL, DMB, DSB, ISB, MRS, MSR). The Cortex-M3 / M4 / M7 / M33 have all base Thumb-1 and Thumb-2 instructions. The Cortex-M3 adds three Thumb-1 instructions, all Thumb-2 instructions, hardware integer divide, and saturation arithmetic instructions. The Cortex-M4 adds DSP instructions and an optional single-precision floating-point unit (VFPv4-SP). The Cortex-M7 adds an optional double-precision FPU (VFPv5).
Note: The Cortex-M0 / M0+ / M1 doesn't include these 16-bit Thumb-1 instructions: CBZ, CBNZ, IT.
Note: The Cortex-M0 / M0+ / M1 only include these 32-bit Thumb-2 instructions: BL, DMB, DSB, ISB, MRS, MSR.
Note: The Cortex-M0 / M0+ / M1 / M23 only has 32-bit multiply instructions with a lower-32-bit result (32bit × 32bit = lower 32bit), where as the Cortex-M3 / M4 / M7 / M33 includes additional 32-bit multiply instructions with 64-bit results (32bit × 32bit = 64bit). The Cortex-M4 / M7 / M33 also include DSP instructions for (16bit × 16bit = 32bit), (32bit × 16bit = upper 32bit), (32bit × 32bit = upper 32bit) multiplications. If a smaller silicon die is required, the Cortex-M0 / M0+ / M1 has an option to be a much slower instruction, though it is rarely implemented in the M0 or M0+.
Note: The Cortex-M4 and M33 has a silicon FPU option of single-precision (SP). The Cortex-M7 has silicon FPU options of single-precision (SP), or both single-precision (SP) and double-precision (DP). If the Cortex-M4 / M7 / M33 has a FPU, then it is known as the Cortex-M4F / Cortex-M7F / Cortex-M33F.
Note: The Cortex-M series includes three new 16-bit Thumb-1 instructions for sleep mode: SEV, WFE, WFI.
Note: The single-precision (SP) FPU instructions are valid in the Cortex-M4/M7/M33 only when the SP FPU option exists in the silicon.
Note: The double-precision (DP) FPU instructions are valid in the Cortex-M7 only when the DP FPU option exists in the silicon.
The ARM architecture for ARM Cortex-M series removed some features from older legacy cores:
The 32-bit ARM instruction set is not included in Cortex-M cores.
Endianness is chosen at silicon implementation in Cortex-M cores. Legacy cores allowed "on-the-fly" changing of the data endian mode.
Co-processors aren't supported on Cortex-M cores.
The capabilities of the 32-bit ARM instruction set is duplicated in many way by the Thumb-1 and Thumb-2 instruction sets, but some ARM features don't have a similar feature:
The SWP and SWPB (swap) ARM instructions don't have a similar feature in Cortex-M.
The 16-bit Thumb-1 instruction set has evolved over time since it was first released in the legacy ARM7T cores with the ARMv4T architecture. New Thumb-1 instructions were added as each legacy ARMv5 / ARMv6 / ARMv6T2 architectures were released. Some 16-bit Thumb-1 instructions were removed from the Cortex-M cores:
"BLX <immediate>" instruction doesn't exist because it was used to switch from Thumb-1 to ARM instruction set. The "BLX <register>" instruction is still available in the Cortex-M.
SETEND doesn't exist because on-the-fly switching of data endian mode is no longer supported.
Co-processor instructions are not supported.
SWI instruction was renamed to SVC instruction, though the instruction binary coding is the same. However, the SVC handler code is different than SWI handler because of changes to the exception models.
The Cortex-M0 core is optimized for small silicon die size and use in the lowest price chips.
Key features of the Cortex-M0 core are:
ARMv6-M architecture
3-stage pipeline.
Instruction sets:
Thumb-1 (most), missing CBZ, CBNZ, IT.
Thumb-2 (some), only BL, DMB, DSB, ISB, MRS, MSR.
32-bit hardware integer multiply with 32-bit result.
1 to 32 interrupts, plus NMI.
Silicon options:
Hardware integer multiply speed: 1-cycle or 32-cycles.
The following microcontrollers are based on the Cortex-M0 core:
Cypress PSoC 4, 4M, 4L
Infineon XMC1000
Nordic nRF51
NXP LPC1100, LPC1200
nuvoTon NuMicro
Sonix SN32F700
STMicroelectronics STM32 F0
Toshiba TX00
Vorago VA10800 (extreme temperature), VA10820 (radiation hardened)
The following chips have a Cortex-M0 as a secondary core:
NXP LPC4300 (one Cortex-M4F + one Cortex-M0)
Texas Instruments SimpleLink Wireless MCUs CC1310 and CC2650 (one programmable Cortex-M3 + one Cortex-M0 network processor + one proprietary Sensor Controller Engine)
The Cortex-M0+ is an optimized superset of the Cortex-M0. The Cortex-M0+ has complete instruction set compatibility with the Cortex-M0 thus allowing the use of the same compiler and debug tools. The Cortex-M0+ pipeline was reduced from 3 to 2 stages, which lowers the power usage. In addition to debug features in the existing Cortex-M0, a silicon option can be added to the Cortex-M0+ called the Micro Trace Buffer (MTB) which provides a simple instruction trace buffer. The Cortex-M0+ also received Cortex-M3 and Cortex-M4 features, which can be added as silicon options, such as the memory protection unit (MPU) and the vector table relocation.
Key features of the Cortex-M0+ core are:
ARMv6-M architecture
2-stage pipeline (one fewer than Cortex-M0).
Instruction sets: (same as Cortex-M0)
Thumb-1 (most), missing CBZ, CBNZ, IT.
Thumb-2 (some), only BL, DMB, DSB, ISB, MRS, MSR.
32-bit hardware integer multiply with 32-bit result.
1 to 32 interrupts, plus NMI.
Silicon options:
Hardware integer multiply speed: 1-cycle or 32-cycles.
8 region memory protection unit (MPU) (same as Cortex-M3 and Cortex-M4).
Vector table relocation (same as Cortex-M3 and Cortex-M4).
Single-cycle I/O port (unique to Cortex-M0+).
Micro Trace Buffer (MTB) (unique to Cortex-M0+).
The following microcontrollers are based on the Cortex-M0+ core:
Atmel SAMD, SAMR, SAML, SAMC
Cypress PSoC 4S, FM0+
Holtek HT32F52xxx
NXP LPC800, LPC11E6x, LPC11U6x
NXP (Freescale) Kinetis E, EA, L, M, V1, W0
Renesas Synergy S1
Silicon Labs (Energy Micro) EFM32 Zero, Happy
STMicroelectronics STM32 L0
Smallest ARM microcontrollers are of the Cortex-M0+ type (as of 2014, smallest at 1.6 mm by 2 mm is Kinetis KL03)
The Cortex-M1 is an optimized core especially designed to be loaded into FPGA chips.
Key features of the Cortex-M1 core are:
ARMv6-M architecture
3-stage pipeline.
Instruction sets:
Thumb-1 (most), missing CBZ, CBNZ, IT.
Thumb-2 (some), only BL, DMB, DSB, ISB, MRS, MSR.
32-bit hardware integer multiply with 32-bit result.
1 to 32 interrupts, plus NMI.
Silicon options:
Hardware integer multiply speed: 3-cycle or 33-cycles.
Optional Tightly-Coupled Memory (TCM): 0 to 1 MB instruction-TCM, 0 to 1 MB data-TCM, each with optional ECC.
External interrupts: 0, 1, 8, 16, 32.
Debug: none, reduced, full.
Data endianness: little-endian or BE-8 big-endian.
OS extension: present or absent.
The following vendors support the Cortex-M1 as soft-cores on their FPGA chips:
Altera Cyclone-II, Cyclone-III, Stratix-II, Stratix-III
Microsemi (Actel) Fusion, IGLOO/e, ProASIC3L, ProASIC3/E
Xilinx Spartan-3, Virtex-2, Virtex-3, Virtex-4
Key features of the Cortex-M3 core are:
ARMv7-M architecture
3-stage pipeline with branch speculation.
Instruction sets:
Thumb-1 (entire).
Thumb-2 (entire).
32-bit hardware integer multiply with 32-bit or 64-bit result, signed or unsigned, add or subtract after the multiply.
32-bit hardware integer divide (2-12 cycles).
saturation arithmetic support.
1 to 240 interrupts, plus NMI.
12 cycle interrupt latency.
Integrated sleep modes.
Silicon options:
Optional Memory Protection Unit (MPU): 0 or 8 regions.
The following microcontrollers are based on the Cortex-M3 core:
Actel SmartFusion, SmartFusion 2
Analog Devices ADuCM3xx
Atmel SAM3A, SAM3N, SAM3S, SAM3U, SAM3X
Cypress PSoC 5, 5LP, FM3
Holtek HT32F
NXP LPC1300, LPC1700, LPC1800
ON Semiconductor Q32M210
Realtek RTL8710
Silicon Labs Precision32
Silicon Labs (Energy Micro) EFM32 Tiny, Gecko, Leopard, Giant
STMicroelectronics STM32 F1, F2, L1, W
Texas Instruments F28, LM3, TMS470, OMAP 4
Texas Instruments SimpleLink Wireless MCUs (CC1310 Sub-GHz and CC2650 BLE+ZigBee+6LoWPAN)
Toshiba TX03
The following chips have a Cortex-M3 as a secondary core:
Apple A9 (Cortex-M3 as integrated M9 motion Co-Processor)
CSR Quatro 5300 (Cortex-M3 as co-processor)
Samsung Exynos 7420 (Cortex-M3 as a DVS microcontroller)
Texas Instruments F28, LM3, TMS470, OMAP 4470 (one Cortex-A9 + two Cortex-M3)
XMOS XS1-XA (seven xCORE + one Cortex-M3)
Conceptually the Cortex-M4 is a Cortex-M3 plus DSP instructions, and optional floating-point unit (FPU). If a core contains an FPU, it is known as a Cortex-M4F, otherwise it is a Cortex-M4.
Key features of the Cortex-M4 core are:
ARMv7E-M architecture
3-stage pipeline with branch speculation.
Instruction sets:
Thumb-1 (entire).
Thumb-2 (entire).
32-bit hardware integer multiply with 32-bit or 64-bit result, signed or unsigned, add or subtract after the multiply.
32-bit hardware integer divide (2-12 cycles).
Saturation arithmetic support.
DSP extension: Single cycle 16/32-bit MAC, single cycle dual 16-bit MAC, 8/16-bit SIMD arithmetic.
1 to 240 interrupts, plus NMI.
12 cycle interrupt latency.
Integrated sleep modes.
Silicon options:
Optional floating-point unit (FPU): single-precision only IEEE-754 compliant. It is called the FPv4-SP extension.
Optional memory protection unit (MPU): 0 or 8 regions.
The following microcontrollers are based on the Cortex-M4 core:
Atmel SAM4L, SAM4N, SAM4S
NXP (Freescale) Kinetis K, W2
The following microcontrollers are based on the Cortex-M4F (M4 + FPU) core:
Atmel SAM4C (dual core), SAM4E, SAMG
Cypress FM4
Infineon XMC4000
Microchip CEC1302
Nordic nRF52
NXP LPC4000, LPC4300 (one Cortex-M4F + one Cortex-M0)
NXP (Freescale) Kinetis K, V3, V4
Renesas Synergy S3, S5, S7
Silicon Labs (Energy Micro) EFM32 Wonder
STMicroelectronics STM32 F3, F4, L4
Texas Instruments LM4F, TM4C, MSP432
Texas Instruments SimpleLink Wi-Fi CC3200 and CC3200MOD (FCC, IC, CE pre-certified module)
Toshiba TX04
The following chips have either a Cortex-M4 or M4F as a secondary core:
NXP (Freescale) Vybrid VF6 (one Cortex-A5 + one Cortex-M4F)
NXP (Freescale) i.MX 6 SoloX (one Cortex-A9 + one Cortex-M4F)
NXP (Freescale) i.MX 7 Solo/Dual (one or two Cortex-A7 + one Cortex-M4F)
Texas Instruments OMAP 5 (two Cortex-A15s + two Cortex-M4)
Texas Instruments Sitara AM57xx (one or two Cortex-A15s + two Cortex-M4s as image processing units + two Cortex-M4s as general purpose units)
The Cortex-M7 is a high-performance core with almost double the power efficiency of the older Cortex-M4. It features a 6-stage superscalar pipeline with branch prediction and an optional floating-point unit capable of single-precision and optionally double-precision operations. The instruction and data buses have been enlarged to 64-bit wide over the previous 32-bit buses. If a core contains an FPU, it is known as a Cortex-M7F, otherwise it is a Cortex-M7.
Key features of the Cortex-M7 core are:
ARMv7E-M architecture.
6-stage pipeline with branch speculation.
Instruction sets:
Thumb-1 (entire).
Thumb-2 (entire).
32-bit hardware integer multiply with 32-bit or 64-bit result, signed or unsigned, add or subtract after the multiply.
32-bit hardware integer divide (2-12 cycles).
Saturation arithmetic support.
DSP extension: Single cycle 16/32-bit MAC, single cycle dual 16-bit MAC, 8/16-bit SIMD arithmetic.
1 to 240 interrupts, plus NMI.
12 cycle interrupt latency.
Integrated sleep modes.
Silicon options:
Optional Floating-Point Unit (FPU): (single precision) or (single and double-precision), both IEEE-754-2008 compliant. It is called the FPv5 extension.
Optional CPU cache: 0 to 64 KB instruction-cache, 0 to 64 KB data-cache, each with optional ECC.
Optional Tightly-Coupled Memory (TCM): 0 to 16 MB instruction-TCM, 0 to 16 MB data-TCM, each with optional ECC.
Optional Memory Protection Unit (MPU): 8 or 16 regions.
Optional Embedded Trace Macrocell (ETM): instruction-only, or instruction and data.
Optional Retention Mode (with ARM Power Management Kit) for Sleep Modes.
The following microcontrollers are based on the Cortex-M7 core:
Atmel SAME70, SAMS70, SAMV70
NXP (Freescale) Kinetis KV5x
STMicroelectronics STM32 F7, STM32 H7
The Cortex-M23 core was announced in October 2016 and based on the newer ARMv8-M architecture that was previously announced in November 2015. Conceptually the Cortex-M23 is similar to a Cortex-M0+ plus integer divide instructions and TrustZone security features, and also has a 2-stage instruction pipeline.
As of January 14, 2016 the "ARM Cortex-M23 ARM Generic User Guide" is not yet available from ARM Holdings, though the "ARM Cortex-M23 Technical Reference Manual" is available.
Key features of the Cortex-M23 core are:
ARMv8-M architecture.
TrustZone security instructions. (not available in Cortex-M0/M0+/M1/M3/M4/M7)
32-bit hardware integer divide (17 cycles). (not available in Cortex-M0/M0+/M1 cores) (slower than Cortex-M3/M4/M7 cores)
TBD.
Silicon options:
Optional Memory Protection Unit (MPU): 0, 4, 8, 12, 16 regions.
Optional Security Attribution Unit (SAU): 0, 4, 8 regions.
TBD.
The following microcontrollers are based on the Cortex-M23 core:
No chips available yet.
Expected future chips from Microchip, Nuvoton, NXP, Renesas, Silicon Labs, STMicroelectronics.
The Cortex-M33 core was announced in October 2016 and based on the newer ARMv8-M architecture that was previously announced in November 2015. Conceptually the Cortex-M33 is similar to a Cortex-M4 plus TrustZone security features, and also has a 3-stage instruction pipeline.
As of January 14, 2017 the "ARM Cortex-M33 Technical Reference Manual" and "ARM Cortex-M33 ARM Generic User Guide" are not yet available from ARM Holdings. Some marketing details has been available, but lacking compared to detailed manuals.
Key features of the Cortex-M33 core are:
ARMv8-M architecture.
TrustZone security instructions. (not available in Cortex-M0/M0+/M1/M3/M4/M7)
32-bit hardware integer divide (17 cycles). (not available in Cortex-M0/M0+/M1 cores) (slower than Cortex-M3/M4/M7 cores)
Stack limit register.
TBD.
Silicon options:
Optional Floating-Point Unit (FPU): single-precision only IEEE-754 compliant. It is called the FPv5 extension.
Optional Memory Protection Unit (MPU): 0, 4, 8, 12, 16 regions.
Optional Security Attribution Unit (SAU): 0, 4, 8 regions.
TBD.
The following microcontrollers are based on the Cortex-M33 core:
No chips available yet.
Expected future chips from Analog Devices, NXP, Renasas, Silicon Labs, STMicroelectronics.
The amount of documentation for all ARM chips is daunting, especially for newcomers. The documentation for microcontrollers from past decades would easily be inclusive in a single document, but as chips have evolved so has the documentation grown. The total documentation is especially hard to grasp for all ARM chips since it consists of documents from the IC manufacturer and documents from CPU core vendor (ARM Holdings).
A typical top-down documentation tree is: manufacturer website, manufacturer marketing slides, manufacturer datasheet for the exact physical chip, manufacturer detailed reference manual that describes common peripherals and aspects of a physical chip family, ARM core generic user guide, ARM core technical reference manual, ARM architecture reference manual that describes the instruction set(s).
Documentation tree (top to bottom)
- IC manufacturer website
- IC manufacturer marketing slides
- IC manufacturer datasheet
- IC manufacturer reference manual
- ARM core website
- ARM core generic user guide
- ARM core technical reference manual
- ARM architecture reference manual
IC manufacturers have additional documents, such as: evaluation board user manuals, application notes, getting started guides, software library documents, errata, and more. See External Links section for links to official ARM documents.
