Sandy Bridge

Updated on Oct 04, 2024

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Max. CPU clock rate 1.60 GHz to 3.60 GHz L1 cache 64 KB per core		Product code 80623 (desktop) L2 cache 256 KB per core

L3 cache 1 MB to 8 MB shared10 MB to 15 MB (Extreme)3 MB to 20 MB (Xeon) Model Celeron SeriesPentium SeriesCore i3/i5/i7/i7 Extreme SeriesXeon E3/E5 Series

Sandy Bridge is the codename for a microarchitecture developed by Intel beginning in 2005 for central processing units in computers to replace the Nehalem microarchitecture. Intel demonstrated a Sandy Bridge processor in 2009, and released first products based on the architecture in January 2011 under the Core brand. Developed primarily by the Israeli branch of Intel, the codename was originally "Gesher" (meaning "bridge" in Hebrew).

Sandy Bridge implementations targeted a 32 nanometer manufacturing process, while Intel's subsequent product, codenamed Ivy Bridge, uses a 22 nanometer process. The Ivy Bridge die shrink, known in the Intel Tick-Tock model as the "tick", is based on FinFET (non-planar, "3D") tri-gate transistors. Intel demonstrated the Ivy Bridge processors in 2011.

A Core i7 2600 Sandy Bridge CPU at 3.4 GHz with 1333MHz DDR3 memory reaches 83 GFLOPS performance in the Whetstone benchmark and 118,000 MIPS in the Dhrystone benchmark.

Technology

Developed primarily by the Israel branch of Intel, the codename was originally "Gesher" (meaning "bridge" in Hebrew). The name was changed to avoid being associated with the defunct Gesher political party; the decision was led by Ron Friedman, vice president of Intel managing the group at the time. Intel demonstrated a Sandy Bridge processor with A1 stepping at 2 GHz during the Intel Developer Forum in September 2009.

Upgraded features from Nehalem include:

Intel Turbo Boost 2.0

32 KB data + 32 KB instruction L1 cache (4 clocks) and 256 KB L2 cache (11 clocks) per core

Shared L3 cache includes the processor graphics (LGA 1155).

64-byte cache line size

Improved 3 integer ALU, 2 vector ALU and 2 AGU per core.

Two load/store operations per CPU cycle for each memory channel

Decoded micro-operation cache (uop cache) and enlarged, optimized branch predictor

Sandy Bridge retains the four branch predictors found in Nehalem: the branch target buffer (BTB), indirect branch target array, loop detector and renamed return stack buffer. Sandy Bridge has a single BTB that holds twice as many branch targets as the L1 and L2 BTBs in Nehalem.

Improved performance for transcendental mathematics, AES encryption (AES instruction set), and SHA-1 hashing

256-bit/cycle ring bus interconnect between cores, graphics, cache and System Agent Domain

Advanced Vector Extensions (AVX) 256-bit instruction set with wider vectors, new extensible syntax and rich functionality.

Intel Quick Sync Video, hardware support for video encoding and decoding

Up to eight physical cores or 16 logical cores through Hyper-threading

Integration of the GMCH (integrated graphics and memory controller) and processor into a single die inside the processor package. In contrast, Sandy Bridge's predecessor, Clarkdale, has two separate dies (one for GMCH, one for processor) within the processor package. This tighter integration reduces memory latency even more.

A 14- to 19-stage instruction pipeline, depending on the micro-operation cache hit or miss

All translation lookaside buffers (TLBs) are 4-way associative.

Models and steppings

All Sandy Bridge processors with one, two, or four cores report the same CPUID model 0206A7h and are closely related. The stepping number can not be seen from the CPUID but only from the PCI configuration space. The later Sandy Bridge-E processors with up to eight cores and no graphics are using CPUIDs 0206D6h and 0206D7h. Ivy Bridge CPUs all have CPUID 0306A9h to date, and are built in four different configurations differing in the number of cores, L3 cache and GPU execution units.

Performance

The average performance increase, according to IXBT Labs and Semi Accurate as well as many other benchmarking sites, at clock to clock is 11.3% compared to the Nehalem Generation, which includes Bloomfield, Clarkdale, and Lynnfield processors.

Around twice the integrated graphics performance compared to Clarkdale's (12 EUs comparison).

List of Sandy Bridge processors

¹Processors featuring Intel's HD 3000 graphics are set in bold. Other processors feature HD 2000 graphics, HD Graphics (Pentium and Celeron models) or no graphics core (Graphics Clock rate indicated by N/A).

This list may not contain all the Sandy Bridge processors released by Intel. A more complete listing can be found on Intel's website.

Suffixes to denote:

K – Unlocked (adjustable CPU ratio up to 57 bins)

P – Versions clocked slightly higher than similar models, but with onboard-graphics deactivated.

S – Performance-optimized lifestyle (low power with 65W TDP)

T – Power-optimized lifestyle (ultra low power with 35-45W TDP)

X – Extreme performance (adjustable CPU ratio with no ratio limit)

NOTE: 3970X, 3960X, 3930K, and 3820 are actually of Sandy Bridge-E edition.

Mobile platform

Core i5-2515E and Core i7-2715QE processors have support for ECC memory and PCI express port bifurcation.

All mobile processors, except Celeron and Pentium, use Intel's Graphics subsystem HD 3000 (12 EUs).

Suffixes to denote:

M – Mobile processors

XM – Unlocked

QM – Quad-core

E – Embedded mobile processors

QE – Quad-core

LE – Performance-optimized

UE – Power-optimized

Cougar Point chipset flaw

On 31 January 2011, Intel issued a recall on all 67-series motherboards due to a flaw in the Cougar Point Chipset. A hardware problem, in which the chipset's SATA II ports may fail over time, cause failure of connection to SATA devices, though data is not at risk. Intel claims that this problem will affect only 5% of users over 3 years, however, heavier I/O workloads can exacerbate the problem.

Intel stopped production of flawed B2 stepping chipsets and began producing B3 stepping chipsets with the silicon fix. Shipping of these new chipsets started on 14 February 2011 and Intel estimated full recovery volume in April 2011. Motherboard manufacturers (such as ASUS and Gigabyte Technology) and computer manufacturers (such as Dell and Hewlett-Packard) stopped selling products that involved the flawed chipset and offered support for affected customers. Options ranged from swapping for B3 motherboards to product refunds.

Sandy Bridge processor sales were temporarily on hold, as one cannot use the CPU without a motherboard. However, processor release dates were not affected. After two weeks, Intel continued shipping some chipsets, but manufacturers had to agree to a set of terms that will prevent customers from encountering the bug.

Overclocking

With Sandy Bridge, Intel has tied the speed of every bus (USB, SATA, PCI, PCI-E, CPU cores, Uncore, memory etc.) to a single internal clock generator issuing the basic 100 MHz Base Clock (BClk). With CPUs being multiplier locked, the only way to overclock is to increase the BClk, which can be raised by only 5–7% without other hardware components failing. As a work around, Intel made available K/X-series processors, which feature unlocked multipliers; with a multiplier cap of 57 for Sandy Bridge. For the Sandy Bridge E platform, there is alternative method known as the BClk ratio overclock.

During IDF (Intel Developer Forum) 2010, Intel demonstrated an unknown Sandy Bridge CPU running stably overclocked at 4.9 GHz on air cooling.

Chipset

Non-K edition CPUs can overclock up to four bins from its turbo multiplier. Refer here for chipset support.

vPro remote-control

Sandy and Ivy Bridge processors with vPro capability have security features that can remotely disable a PC or erase information from hard drives. This can be useful in the case of a lost or stolen PC. The commands can be received through 3G signals, Ethernet, or Internet connections. AES encryption acceleration will be available, which can be useful for video conferencing and VoIP applications.

Intel Insider

Sandy and Ivy Bridge processors contain a DRM technology that some video streaming web sites rely on to restrict use of their content. Such web sites offer 1080p streaming to users with such CPUs and downgrade the quality for other users.

Software development kit

With the introduction of the Sandy Bridge microarchitecture, Intel also introduced the Intel Data Plane Development Kit (Intel DPDK) to help developers of communications applications take advantage of the platform in packet processing applications, and network processors.

Roadmap

Intel demonstrated the Haswell architecture in September 2011, released in 2013 as the successor to Sandy Bridge and Ivy Bridge.

References

Sandy Bridge Wikipedia

(Text) CC BY-SA

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