KOMDIV 64

Updated on Dec 19, 2024

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Produced 2007 Max. CPU clock rate 200 MHz to 1 GHz Instruction set MIPS IV		Designed by NIISI Min. feature size 65 nm to 0.35 μm Cores 1 to 2

The KOMDIV-64 (Russian: КОМДИВ-64) is a family of 64-bit microprocessors developed by the Scientific Research Institute of System Development (NIISI) of the Russian Academy of Sciences and manufactured by TSMC, UMC, GlobalFoundries, and X-Fab. The KOMDIV-64 processors are intended primarily for industrial and high-performance computing applications.

These microprocessors implement the MIPS IV instruction set architecture (ISA).

1890VM5F

0.35 μm CMOS process

16 KB L1 instruction cache, 16 KB L1 data cache, 256 KB L2 cache

in-order, dual-issue superscalar; 5-stage integer pipeline, 7-stage floating point pipeline

26.6 million transistors

compatible with PMC-Sierra RM7000

performance is 0.9 dhrystones/MHz, 1.32 whetstones/MHz, 1.09 coremarks/MHz

0.18 μm CMOS process

16 KB L1 instruction cache, 16 KB L1 data cache, 256 KB L2 cache

680-pin BGA

System-on-a-chip (SoC) including a PCI controller, 5 64-bit timers, RapidIO, Ethernet 100/10 Mbit/s, USB 2.0, I²C

0.18 μm CMOS process

16 KB L1 instruction cache, 16 KB L1 data cache, 32 KB general-purpose SRAM

680-pin BGA

System-on-a-chip (SoC) including a PCI controller, 3 64-bit timers, RapidIO, I²C, SPI, 128-bit DSP with 4 cores and 64 KB RAM per core

65 nm CMOS process

32 KB L1 instruction cache, 16 KB L1 data cache, 512 KB L2 cache

1294-pin BGA

System-on-a-chip (SoC) including a PCI controller, 5 64-bit timers, RapidIO, Ethernet 1000/100/10 Mbit/s, USB 2.0, I²C, SPI, SATA 3.0

production start in 2015 at TSMC

65 nm CMOS process

dual core, clock rate 1 GHz

1294-pin BGA

System-on-a-chip (SoC) including RapidIO, Ethernet 1000 Mbit/s, USB 2.0, SATA 3.0

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