Name Ian Young | ||
Citizenship United States, Australia Thesis MOS switched-capacitor analog sampled-data recursive filters (1978) Known for Intel Microprocessor Clock Scaling from 50 MHz to 3 GHz, Analog MOS Circuits, Phase-locked loop Influences Semiconductor Research Corporation Notable awards Fellow, IEEE 1999; Intel Achievement Awards (3 times), Fellow Intel 1996, Senior Fellow Intel 2004 Residence Hillsboro, Oregon, United States Doctoral advisor David A. Hodges, Paul R Gray | ||
Ian. A. Young is an Intel engineer . Young is a co-inventor of the design for an oscillator used in Intel microprocessors Young was a co-inventor on Intel BiCMOS logic circuit family, adopted in Pentium, Pentium Pro, Pentium II microprocessors. Young also developed microprocessor performance optimization metric for transistors (Front End Transistor Metric) and interconnects, . Young has written 50 research papers and 71 patents in switched capacitor circuits, DRAM, SRAM, BiCMOS, x86 clocking, Photonics and spintronics.
Contents
- Biography
- Early Career Analog MOS Integrated Circuits Switched Capacitor Filters
- Intel BiCMOS for Logic SRAM
- Pentium Era and Clock Scaling
- Interconnects photonics
- Beyond CMOS Computing
- Awards and honors
- Selected works
- Selected Patents
- References
Biography
Born in Melbourne, Australia, Young received his bachelor's and master's degrees in electrical engineering from the University of Melbourne, Australia. He received his Ph.D. in electrical engineering from the University of California, Berkeley in 1978, where he did research on MOSFET switched-capacitor filters. Prior to Intel, he worked on analog/digital integrated circuits for telecommunications products at Mostek Corporation.
Early Career, Analog MOS Integrated Circuits & Switched Capacitor Filters
Young obtained his PhD from University of California, Berkeley in 1978 working with David A. Hodges developing the first switched MOS capacitor circuits which later developed into analog MOS switched capacitor filters. In 1977, Young (then a Ph.D. student) with David A. Hodges and Paul Gray (at Berkeley) demonstrated an All-MOS sampled-data second-order active filter using a precise clock reference, four operational amplifiers, analog switches and ratioed capacitors all fabricated on an NMOS integrated circuit.
Intel BiCMOS for Logic & SRAM
Young started at Intel in 1983 with the development of circuits for the world’s first 1 Mb DRAM in 1 μm CMOS in 1985, and first 64 K SRAM in 1 μm CMOS. This was also the first military qualified SRAM under the VHIC program. At 600 nanometer node, Intel adopted BiCMOS for logic requiring the development of a BiCMOS SRAM for cache and a new family of standard logic circuits.
The BiCMOS logic family employed the npn devices in the pull-up path of the BiCMOS gate, to form a low power CMOS logic family with high capacitive drive capability. Intel's BiCMOS technology was enabled by an innovative triple diffused npn transistor. This led to a highly manufacturable low cost process due to minimum number of additional process steps. In contrast, other companies employed BiCMOS to implement Emitter-coupled logic for microprocessors, which consumed much more power. The BiCMOS circuits were developed for the Pentium processor family and its follow-on generations Pentium Pro, Pentium II processor family.
Pentium Era and Clock Scaling
Young developed the original Phase Locked Loop (PLL) based clocking circuit in a microprocessor while working on the 50 MHz Intel 80486 processor design. He subsequently developed the core PLL clocking circuit building blocks used in each generation of Intel microprocessors through the 0.13 μm 3.2 GHz Pentium 4. The successful introduction of GHz clocking contributed to massive improvements in computing power.
The Clock rate scaling ushered by Intel and AMD ended as the thermal power dissipation of processors reached 100 W/cm^2. By the end of the race for clock speed, the clock rates have increased by more than a factor of 50. Intel subsequently shifted to multi-core era with modified Intel Core architecture and concurrent improvements in cache sizes to take advantage of the continued success of Moore's law.
Interconnects & photonics
In 2001, as single end signaled aluminum interconnects have reached the technology scaling limits, Young and co-workers quantified the migration to repeated electrical interconnects for mainstream microprocessors. Repeated electrical interconnects are now widely adopted for Intel process technology.
From 2001 to 2010, he led a circuit design team doing research and development of analog mixed-signal high-speed serial I/O circuits for microprocessors and wireless RF CMOS synthesizers and transceiver circuits, in conjunction with the development of Intel’s 90 nm to 22 nm process technology. Since 1999, Young has also led research to enable Optical I/O for microprocessors demonstrating the first CMOS compatible Back end of line optical technology adopting Photonic integrated circuit for enabling tera-scale optical links for CMOS computing.
Beyond CMOS Computing
Recent work has developed a uniform bench marking to identify the technology options in spintronics, Tunnel junction and photonics, devices. He is a longstanding mentor of FCRP. Young is an Intel representative at International Technology Roadmap for Semiconductors He is also the founding editor-in-chief of IEEE Journal of Exploratory Solid State Computational Devices.