Cycles per instruction

Definition

Cycles Per Instruction is defined by the following:

C P I = Σ i ( I C i ) ( C C i ) I C

Where I C i is the number of instructions for a given instruction type i , C C i is the clock-cycles for that instruction type and I C = Σ i ( I C i ) is the total instruction count. The summation sums over all instruction types for a given benchmarking process.

Explanation

Let us assume a classic RISC pipeline, with the following 5 stages:

1. Instruction fetch cycle (IF).
2. Instruction decode/Register fetch cycle (ID).
3. Execution/Effective address cycle (EX).
4. Memory access (MEM).
5. Write-back cycle (WB).

Each stage requires one clock cycle and an instruction passes through the stages sequentially. Without pipelining, a new instruction is fetched in stage 1 only after the previous instruction finishes at stage 5, therefore the number of clock cycles it takes to execute an instruction is 5 (CPI = 5 > 1). In this case, the processor is said to be subscalar. With pipelining, a new instruction is fetched every clock cycle by exploiting instruction-level parallelism, therefore, since one could theoretically have 5 instructions in the 5 pipeline stages at once (one instruction per stage), a different instruction would complete stage 5 in every clock cycle and on average the number of clock cycles it takes to execute an instruction is 1 (CPI = 1). In this case, the processor is said to be scalar.

With a single-execution-unit processor, the best CPI attainable is 1. However, with a multiple-execution-unit processor, one may achieve even better CPI values (CPI < 1). In this case, the processor is said to be superscalar. To get better CPI values without pipelining, the number of execution units must be greater than the number of stages. For example, with 6 executions units, 6 new instructions are fetched in stage 1 only after the 6 previous instructions finish at stage 5, therefore on average the number of clock cycles it takes to execute an instruction is 5/6 (CPI = 5/6 < 1). To get better CPI values with pipelining, there must be at least 2 execution units. For example, with 2 executions units, 2 new instructions are fetched every clock cycle by exploiting instruction-level parallelism, therefore 2 different instructions would complete stage 5 in every clock cycle and on average the number of clock cycles it takes to execute an instruction is 1/2 (CPI = 1/2 < 1).

Example 1

For the multi-cycle MIPS, there are 5 types of instructions:

If a program has:

then, the CPI is:

CPI = 5 × 50 + 4 × 15 + 4 × 25 + 3 × 8 + 3 × 2 100 = 4.4

Example 2

A 400-MHz processor was used to execute a benchmark program with the following instruction mix and clock cycle count:

Determine the effective CPI, MIPS (Millions of instructions per second)rate, and execution time for this program.

CPI = 45000 × 1 + 32000 × 2 + 15000 × 2 + 8000 × 2 100000 = 155000 100000 = 1.55

400 M h z = 400 , 000 , 000 H z

since: M I P S ∝ 1 / C P I and M I P S ∝ c l o c k F r e q e u n c y

Effective processor performance = MIPS = clock frequency CPI × 1 1 Million = 400 , 000 , 000 1.55 × 1000000 = 400 1.55 = 258 MIPS

Therefore:

Execution time ( T ) = CPI × Instruction count × clock time = CPI × Instruction Count frequency = 1.55 × 100000 400 × 1000000 = 1.55 4000 = 0.0003875 ms