Trisha Shetty (Editor)

ARM Cortex A53

Updated on
Edit
Like
Comment
Share on FacebookTweet on TwitterShare on LinkedInShare on Reddit
Designed by
  
ARM Holdings

Cores
  
1–4 per cluster

L2 cache
  
128 KB–2 MB

Microarchitecture
  
ARMv8-A

L1 cache
  
8–64 KB

The ARM Cortex-A53 is a microarchitecture implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings. The Cortex-A53 is a superscalar processor capable of dual-issuing some instructions. It is available as SIP core to licensees, and is marketed by ARM as either a stand-alone, more energy-efficient alternative to the more powerful Cortex-A57 microarchitecture, or to be used alongside a more powerful microarchitecture in a big.LITTLE configuration.

Contents

Overview

  • 8-stage pipelined processor with 2-way superscalar, in-order execution pipeline
  • DSP and NEON SIMD extensions are mandatory per core
  • VFPv4 Floating Point Unit onboard (per core)
  • Hardware virtualization support
  • TrustZone security extensions
  • 64-byte cache lines
  • 10-entry L1 TLB, and 512-entry L2 TLB
  • 4 Kb conditional branch predictor, 256-entry indirect branch predictor

    • Utilization

    ARM Cortex-A53 processor has been used in Raspberry Pi 3 since February 2016.

    References

    ARM Cortex-A53 Wikipedia
    (Text) CC BY-SA


    Similar Topics