Designer Qualcomm Introduced 2006 (QDSP6) | Bits 32-bit Type Register-Register | |
Design 4-way multithreaded VLIW Encoding Fixed 4 byte per instruction, up to 4 instructions in VLIW multiinstruction | ||
Hexagon (QDSP6) is the brand for a family of 32-bit multi-threaded microarchitectures implementing the same instruction set for a digital signal processor (DSP) developed by Qualcomm. According to 2012 estimation, Qualcomm shipped 1.2 billion DSP cores inside its system on a chip (SoCs) (average 2.3 DSP core per SoC) in 2011 year, and 1.5 billion cores were planned for 2012, making the QDSP6 the most shipped architecture of DSP (CEVA had around 1 billion of DSP cores shipped in 2011 with 90% of IP-licenseable DSP market).
Contents
- Operating systems
- Compilers
- Adoption of the SIP block
- Third party integration
- Versions
- Availability in Snapdragon products
- Code sample
- References
The Hexagon architecture is designed to deliver performance with low power over a variety of applications. It has features such as hardware assisted multithreading, privilege levels, Very Long Instruction Word (VLIW), Single Instruction, Multiple Data (SIMD), and instructions geared toward efficient signal processing. The CPU is capable of in-order dispatching up to 4 instructions (the packet) to 4 Execution Units every clock. Hardware multithreading is implemented as barrel temporal multithreading - threads are switched in round-robin fashion each cycle, so the 600 MHz physical core is presented as three logical 200 MHz cores before V5. Hexagon V5 switched to dynamic multithreading (DMT) with thread switch on L2 misses, interrupt waiting or on special instructions.
Operating systems
The port of Linux for Hexagon runs under a hypervisor layer ("Hexagon Virtual Machine") and was merged with the 3.2 release of the kernel. The original hypervisor is closed-source, and in April 2013 a minimal open-source hypervisor implementation for QDSP6 V2 and V3, the "Hexagon MiniVM" was released by Qualcomm under a BSD-style license.
Compilers
Support for Hexagon was added in 3.1 release of LLVM by Tony Linthicum. There is also a non-FSF maintained branch of GCC and binutils.
Adoption of the SIP block
Qualcomm Hexagon DSPs have been available in Qualcomm Snapdragon SoC since 2006. In Snapdragon S4 (MSM8960 and newer) there are three QDSP cores, two in the Modem subsystem and one Hexagon core in the Multimedia subsystem. Modem cores are programmed by Qualcomm only, and only Multimedia core is allowed to be programmed by user.
They are also used in some femtocell processors of Qualcomm, including FSM9832.
Third party integration
In March 2016, it was announced that semiconductor company Conexant's AudioSmart audio processing software was being integrated into Qualcomm's Hexagon.
Versions
There are six versions of QDSP6 architecture released: V1 (2006), V2 (2007–2008), V3 (2009), V4 (2010–2011), QDSP6 V5 (2013, in Snapdragon 800); and QDSP6 V6 (2016, in Snapdragon 820). V4 has 20 DMIPS per milliwatt, operating at 500 MHz. Clock speed of Hexagon varies in 400–2000 MHz for QDSP6 and in 256–350 MHz for previous generation of the architecture, the QDSP5.
Availability in Snapdragon products
Both Hexagon (QDSP6) and pre-Hexagon (QDSP5) cores are used in modern Qualcomm SoCs, QDSP5 mostly in low-end products. Modem QDSPs (often pre-Hexagon) are not shown in the table.
QDSP5 usage:
QDSP6 (Hexagon) usage:
Code sample
This is a single instruction packet from the inner loop of a FFT:
{ R17:16 = MEMD(R0++M1) MEMD(R6++M1) = R25:24 R20 = CMPY(R20, R8):<<1:rnd:sat R11:10 = VADDH(R11:10, R13:12) }:endloop0This packet is claimed by Qualcomm to be equal to 29 classic RISC operations; it includes vector add (4x 16-bit), complex multiply operation and hardware loop support. All instructions of the packet are done in the same cycle.