Girish Mahajan (Editor)

Preesm

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Initial release
  
2008

Type
  
Rapid Prototyping Tool

Development status
  
Active

Preesm

Developer(s)
  
PREESM Development Team at IETR

Written in
  
Java as Eclipse plug-ins

License
  
CeCILL-B or CeCILL-C depending on the plug-ins

PREESM (the Parallel and Real-time Embedded Executives Scheduling Method) is an open source rapid prototyping and code generation tool. It is primarily employed to simulate signal processing applications and generate code for multi-core Digital Signal Processors. PREESM is developed at the Institute of Electronics and Telecommunications-Rennes (IETR) in collaboration with Texas Instruments France in Nice.

Contents

The PREESM tool inputs are an algorithm graph, an architecture graph, and a scenario which is a set of parameters and constraints that specify the conditions under which the deployment will run. The chosen type of algorithm graph is a hierarchical extension of Synchronous Dataflow (SDF) graphs named Interface-Based hierarchical Synchronous Dataflow (IBSDF). The architecture graph is named System-Level Architecture Model (S-LAM). From these inputs, PREESM maps and schedules automatically the code over the multiple processing elements and generates multi-core code.

Documentation

Online documentation is provided in the PREESM SourceForge Website.

Publications

  • Desnos, Karol; Pelcat, Maxime; Nezan, Jean-François; Aridhi, Slaheddine (2012). "Memory Bounds for the Distributed Execution of a Hierarchical Synchronous Data-Flow Graph" (PDF). Proceedings 2012 International Conference on Embedded Computer Systems: Architecture, Modeling and Simulation (SAMOS XII). 
  • Pelcat, Maxime; Nezan, Jean-François; Piat, Jonathan; Aridhi, Slaheddine (2012). Springer, ed. Physical Layer Multicore Prototyping: A Dataflow-Based Approach for LTE eNodeB. 
  • Piat, Jonathan (2010). "Data flow modelling and optimization of loops for multi-core architectures" (PDF). PhD Thesis, INSA de Rennes. 
  • Pelcat, Maxime (2010). "Rapid Prototyping and Dataflow-Based Code Generation for the 3GPP LTE eNodeB Physical Layer mapped onto Multi-Core DSPs" (PDF). PhD Thesis, INSA de Rennes. 
  • Pelcat, Maxime; Piat, Jonathan; Wipliez, Matthieu; Aridhi, Slaheddine; Nezan, Jean-François (2009). "An Open Framework for Rapid Prototyping of Signal Processing Applications". EURASIP Journal on Embedded Systems. 
  • Piat, Jonathan; Bhattacharyya, Shuvra S.; Pelcat, Maxime; Raulet, Mickaël (2009). "Multi-Core Code Generation From Interface Based Hierarchy" (PDF). DASIP Sophia Antipolis. 
  • Pelcat, Maxime; Nezan, Jean-François; Piat, Jonathan; Croizer, Jérôme; Aridhi, Slaheddine (2009). "A System-Level Architecture Model for Rapid Prototyping of Heterogeneous Multicore Embedded Systems" (PDF). DASIP Sophia Antipolis. 
  • Piat, Jonathan; Bhattacharyya, Shuvra S.; Raulet, Mickaël (2009). "Interface-based hierarchy for synchronous data-flow graphs" (PDF). SiPS Tampere. 
  • Pelcat, Maxime; Menuet, Pierrick; Aridhi, Slaheddine; Nezan, Jean-François (2009). "Scalable compile-time scheduler for multi-core architectures" (PDF). DATE Nice. 

    • References

    Preesm Wikipedia
    (Text) CC BY-SA