Power estimation techniques for RTL

Introduction

The most accurate power analysis tools are available for the circuit level but unfortunately, even with switch- rather than device-level modelling, tools at the circuit level have disadvantages like they are either too slow or require too much memory thus inhibiting large chip handling. The majority of these are simulators like SPICE and have been used by the designers for many years as performance analysis tools. Due to these disadvantages, gate-level power estimation tools have begun to gain some acceptance where faster, probabilistic techniques have begun to gain a foothold. But it also has its trade off as speedup is achieved on the cost of accuracy, especially in the presence of correlated signals. Over the years it has been realized that biggest wins in low power design cannot come from circuit- and gate-level optimizations whereas architecture, system, and algorithm optimizations tend to have the largest impact on power consumption. Therefore, there has been a shift in the incline of the tool developers towards high-level analysis and optimization tools for power.

Contents

• Introduction
• Motivation
• Advantages of doing power estimation at RTL or architectural level
• Architecture Level Tools
• Gate Equivalents
• Examples of Gate Equivalent technique
• Precharacterized Cell Libraries
• Example
• References

Motivation

It is well known that more significant power reductions are possible if optimizations on higher levels of abstraction are made like the architectural and algorithmic level than at the circuit or gate level. This provides the required motivation for the developers to focus on the development of new architectural level power analysis tools. This in no way imply that lower level tools are unimportant. Instead, each layer of tools provides a foundation upon which the next level can be built. The abstractions of the estimation techniques at a lower level can be used to higher level and applied again with slight modifications.

Advantages of doing power estimation at RTL or architectural level

Architecture-Level Tools

There are two primary techniques for architectural power analysis:

Gate Equivalents

It is a technique based on the concept of gate equivalents. The complexity of a chip architecture can be described approximately in terms of gate equivalents where gate equivalent count specifies the average number of reference gates that are required to implement the particular function.The total power required for the particular function is estimated by multiplying the approximated number of gate equivalents with the average power consumed per gate. The reference gate can be any gate e.g. 2-input NAND gate.

Examples of Gate Equivalent technique

Precharacterized Cell Libraries

This technique further customizes the power estimation of various functional blocks by having separate power model for logic, memory, and interconnect suggesting a Power Factor Approximation (PFA) method for individually characterizing an entire library of functional blocks such as multipliers, adders, etc. instead of a single gate-equivalent model for “logic” blocks.
The power over the entire chip is approximated by the expression:

Where K_i is PFA proportionality constant that characterizes the i_th functional element,G_i is the measure of hardware complexity, and f_i denotes the activation frequency.

Example

G_i denoting the hardware complexity of the multiplier is related to the square of the input word length i.e. N² where N is the word length.The activation frequency is the rate at which multiplies are performed by the algorithm denoted by f_mult and the PFA constant, K_mult, is extracted empirically from past multiplier designs and shown to be about 15 fW/bit2-Hz for a 1.2 µm technology at 5V. The resulting power model for the multiplier on the basis of the above assumptions is:

Advantages:

Weakness:

The estimation error (relative to switch-level simulation) for a 16x16 multiplier is experimented and it is observed that when the dynamic range of the inputs doesn’t fully occupy the word length of the multiplier, the UWN model becomes extremely inaccurate. Granted, good designers attempt to maximize word length utilization. Still, errors in the range of 50-100% are not uncommon. The figure clearly suggests a flaw in the UWN model.