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In electronics, pass transistor logic (PTL) describes several logic families used in the design of integrated circuits. It reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Transistors are used as switches to pass logic levels between nodes of a circuit, instead of as switches connected directly to supply voltages. This reduces the number of active devices, but has the disadvantage that the difference of the voltage between high and low logic levels decreases at each stage. Each transistor in series is less saturated at its output than at its input. If several devices are chained in series in a logic path, a conventionally constructed gate may be required to restore the signal voltage to the full value. By contrast, conventional CMOS logic switches transistors so the output connects to one of the power supply rails, so logic voltage levels in a sequential chain do not decrease. Simulation of circuits may be required to ensure adequate performance.
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Applications
Pass transistor logic often uses fewer transistors, runs faster, and requires less power than the same function implemented with the same transistors in fully complementary CMOS logic.
XOR has the worst-case Karnaugh map -- if implemented from simple gates, it requires more transistors than any other function. The designers of the Z80 and many other chips saved a few transistors by implementing the XOR using pass-transistor logic rather than simple gates.
Basic principles of pass transistor circuits
The pass transistor is driven by a periodic clock signal and acts as an access switch to either charge up or charge down the parasitic capacitance Cx, depending on the input signal Vin. Thus, the two possible operations when the clock signal is active (CK = 1) are the logic "1" transfer (charging up the capacitance Cx to a logic-high level) and the logic "0" transfer (charging down the capacitance Cx to a logic-low level). In either case, the output of the depletion load nMOS inverter obviously assumes a logic-low or a logic-high level, depending upon the voltage Vx.
Complementary pass transistor logic
Some authors use the term "complementary pass transistor logic" to indicate a style of implementing logic gates that uses transmission gates composed of both NMOS and PMOS pass transistors.
Other authors use the term "complementary pass transistor logic" (CPL) to indicate a style of implementing logic gates where each gate consists of a NMOS-only pass transistor network, followed by a CMOS output inverter.
Other authors use the term "complementary pass transistor logic" (CPL) to indicate a style of implementing logic gates using dual-rail encoding. Every CPL gate has two output wires, both the positive signal and the complementary signal, eliminating the need for inverters.
Complementary pass transistor logic or "Differential pass transistor logic" refers to a logic family which is designed for certain advantage. It is common to use this logic family for multiplexers and latches.
CPL uses series transistors to select between possible inverted output values of the logic, the output of which drives an inverter The CMOS transmission gates consist of nMOS and pMOS transistor connected in parallel.
Other forms
Static and dynamic types of pass transistor logic exist, with differing properties with respect to speed, power and low-voltage operation. As integrated circuit supply voltages decrease, the disadvantages of pass transistor logic become more significant; the threshold voltage of transistors becomes large compared to the supply voltage, severely limiting the number of sequential stages. Because complementary inputs are often required to control pass transistors, additional logic stages are required.