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PHY (chip)

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Phy chip


PHY is an abbreviation for the physical layer of the OSI model and refers to the circuitry required to implement physical layer functions.

Contents

PHY (chip) DDR SDRAM PHY IP Denali Software

A PHY connects a link layer device (often called MAC as an abbreviation for media access control) to a physical medium such as an optical fiber or copper cable. A PHY device typically includes a Physical Coding Sublayer (PCS) and a Physical Medium Dependent (PMD) layer. The PCS encodes and decodes the data that is transmitted and received. The purpose of the encoding is to make it easier for the receiver to recover the signal.

PHY (chip) TKJ Electronics Ethernet on STM32F4DISCOVERY using external PHY

Example uses

PHY (chip) SinglePort TripleSpeed Ethernet OnBoard PHY Chip Reference Design

  • Wireless LAN or Wi-Fi: The PHY portion consists of the RF, mixed-signal and analog portions, that are often called transceivers, and the digital baseband portion that use digital signal processor (DSP) and communication algorithm processing, including channel codes. It is common that these PHY portions are integrated with the media access control (MAC) layer in System-on-a-chip (SOC) implementations. Other similar wireless applications are 3G/4G/LTE, WiMAX, UWB, etc.
  • Ethernet: A PHY chip (PHYceiver) is commonly found on Ethernet devices. Its purpose is to provide analog signal physical access to the link. It is usually used in conjunction with a Media Independent Interface (MII) chip or interfaced to a microcontroller that takes care of the higher layer functions.
  • Universal Serial Bus (USB): A PHY chip is integrated into most USB controllers in hosts or embedded systems and provides the bridge between the digital and modulated parts of the interface.
  • IrDA: The Infrared Data Associations (IrDA) specification includes an IrPHY specification for the physical layer of the data transport.
  • Serial ATA (SATA): Serial ATA controllers like the VIA Technologies VT6421 use a PHY.
  • SDRAM chip interfaces
  • Flash memory chip interfaces

    • Ethernet physical transceiver

    PHY (chip) SemiWikicom Synopsys MIPI MPHY in 28nm introduction supporting

    The Ethernet PHY is a component that operates at the physical layer of the OSI network model. It implements the Ethernet physical layer portion of the 1000BASE-T, 100BASE-TX, and 10BASE-T standards.

    More specifically, the Ethernet PHY is a chip that implements the hardware send and receive function of Ethernet frames; it interfaces between the analog domain of Ethernet's line modulation and the digital domain of link-layer packet signaling. The PHY usually does not handle MAC addressing, as that is the link layer's job. Similarly, Wake-on-LAN and Boot ROM functionality is implemented in the network interface card (NIC), which may have PHY, MAC and other functionality integrated into one chip or as separate chips.

    Examples include the Vitesse Semiconductor SimpliPHY and SynchroPHY VSC82xx/85xx/86xx family and Marvell Alaska 88E1310/88E1310S/88E1318/88E1318S Gigabit Ethernet transceivers.

    An Ethernet physical transceiver can also be referred to as a physical layer transmitter and/or receiver, a physical layer transceiver, a PHY transceiver, a PHYceiver, or simply a PHY. The term PHYceiver is often shown as being TM (Trade Marked) but is not currently registered with TESS United States Patent and Trademark Office.

    References

    PHY (chip) Wikipedia
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