The Open NAND Flash Interface Working Group (ONFI or ONFi with a lower case "i"), is a consortium of technology companies working to develop open standards for NAND flash memory and devices that communicate with them. The formation of ONFI was announced at the Intel Developer Forum in March 2006.
The group's goals did not include the development of a new consumer flash memory card format. Rather, ONFI seeks to standardize the low-level interface to raw NAND flash chips, which are the most widely used form of non-volatile memory integrated circuits (chips); in 2006, nearly one trillion MiB of flash memory was incorporated into consumer electronics, and production was expected to double by 2007. As of 2006, NAND flash memory chips from most vendors used similar packaging, had similar pinouts, and accepted similar sets of low-level commands. As a result, when more capable and inexpensive models of NAND flash become available, product designers can incorporate them without major design changes. However, "similar" operation is not optimal: subtle differences in timing and command set mean that products must be thoroughly debugged and tested when a new model of flash chip is used in them. When a flash controller is expected to operate with various NAND flash chips, it must store a table of them in its firmware so that it knows how to deal with differences in their interfaces. This increases the complexity and time-to-market of flash-based devices, and means they are likely to be incompatible with future models of NAND flash, unless and until their firmware is updated.
Thus, one of the main motivations for standardization of NAND flash was to make it easier to switch between NAND chips from different producers, thereby permitting faster development of NAND-based products and lower prices via increased competition among manufacturers. By 2006, NAND flash became increasingly a commodity product, like SDRAM or hard disk drives. It is incorporated into many personal computer and consumer electronics products such as USB flash drives, MP3 players, and solid-state drives. Product designers wanted newer NAND flash chips, for example, to be as easily interchangeable as hard disks from different manufacturers.
The effort to standardize NAND flash may be compared to earlier standardization of electronic components. For example, the 7400 series of TTL digital integrated circuits were originally produced by Texas Instruments, but had become a de facto standard family by the late 1970s. These ICs are manufactured as commodity parts by a number of different vendors. This has allowed designers to freely mix 7400 components from different vendors—and even to mix components based on different logic families, once the 74HCT sub-family become available (consisting of CMOS components with TTL-compatible logic levels).
The ONFI consortium included manufacturers of NAND flash memory such as Hynix, Intel, Micron Technology, Phison, SanDisk, Sony and Spansion. Samsung the world largest manufacturer of NAND flash, were absent in 2006. Vendors of NAND flash-based consumer electronics and computing products are also members.
ONFI produced specifications for standard interface to NAND flash chips.
Version 1.0 of this specification was released on December 28, 2006, and made available at no cost from the ONFI web site. Samsung was still not a participant. It specified:a standard physical interface (pinout) for NAND flash in TSOP-48, WSOP-48, LGA-52, and BGA-63 packages
a standard mechanism for NAND chips to identify themselves and describe their capabilities (comparable to the Serial Presence Detection feature of SDRAM modules)
a standard command set for reading, writing, and erasing NAND flash
standard timing requirements for NAND flash
improved performance via a standard implementation of read cache and increased concurrency for NAND flash operations
improved data integrity by allowing optional error-correcting code (ECC) features
Version 2.0 in February 2008 defined an interface for rates greater than 133 MB/s, whereas the legacy NAND interface was limited to 50 MB/s.
Version 2.1 in January 2009 added features for higher rates of 166 MB/s and 200 MB/s, plus other enhancements to increase power, performance, and ECC capabilities. A verification product was announced in June 2009.
Version 2.2 on October 2009 added: - Individual LUN reset - Enhanced program page register clear - New Icc specs and measurement LUN reset and page register clear enable more efficient operation in larger systems with many NAND devices, while the standardized Icc testing and definitions will provide simplified vendor testing and improved data consistency
ONFI created the Block Abstracted NAND addendum specification to simplify host controller design by relieving the host of the complexities of ECC, bad block management, and other low-level NAND management tasks. The ONFI Block Abstracted NAND revision 1.1 specification adds the high speed source synchronous interface, which provides up to a 5X improvement in bandwidth compared with the traditional asynchronous NAND interface.
The NAND Connector Specification was ratified in April 2008. It specifies a standardized connection for NAND modules (similar to DRAM DIMMs) for use in applications like caching and solid-state drives (SSDs) in PC platforms.
Version 2.3 was published in August 2010. It included a protocol called EZ-NAND that hid ECC details.
Version 3.0, published in March 2011, promoted a high-speed NAND Flash interface supporting transfer rates up to 400 MB/s. It required fewer chip-enable pins enabling more efficient printed circuit board routing. A standard developed jointly with the JEDEC was published in October 2012.
Version 3.2, published on July 23, 2013, raised the data rate to 533 MB/s.