Puneet Varma (Editor)

MyHDL

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MyHDL is a Python based hardware description language (HDL).

Features of MyHDL include:

  • The ability to generate VHDL and Verilog code from a MyHDL design.
  • The ability to generate a testbench (Conversion of test benches) with test vectors in VHDL or Verilog, based on complex computations in Python.
  • The ability to convert a lists of signals.
  • The ability to convert output verification.
  • The ability to do Co-simulation with Verilog.
  • An advanced datatype system, independent of traditional datatypes. MyHDL's translator tool automatically writes conversion functions when the target language requires them.

    • MyHDL is developed by Jan Decaluwe.

    Conversion Examples

    Here, you can see some examples of conversions from MyHDL designs to VHDL and/or Verilog.

    A small combinatorial design

    The example is a small combinatorial design, more specifically the binary to Gray code converter:

    You can create an instance and convert to Verilog and VHDL as follows:

    The generated Verilog code looks as follows:

    The generated VHDL code looks as follows:

    References

    MyHDL Wikipedia
    (Text) CC BY-SA