Puneet Varma (Editor)

MCST R500S

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Produced
  
2007

Max. CPU clock rate
  
500 MHz

Cores
  
2

Common manufacturer(s)
  
TSMC

Instruction set
  
SPARC V8

Designed by
  
Moscow Center of SPARC Technologies (MCST)

The MCST R500S (Russian: МЦСТ R500S) is a 32-bit system-on-a-chip, developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC.

MCST R500S Highlights

  • implements the SPARC V8 instruction set architecture (ISA)
  • dual-core
  • the two cores can work in redundancy to increase reliability of the system.
  • core specifications:
  • in-order, single-issue
  • 5-stage integer pipeline
  • 7-stage floating-point pipeline
  • 16 KB L1 instruction cache
  • 32 KB L1 data cache
  • shared 512KB L2 cache
  • integrated controllers:
  • memory
  • PCI
  • RDMA (to connect with other MCST R500S)
  • MSI (Mbus and SBus)
  • EBus
  • PS/2
  • Ethernet 100
  • SCSI-2
  • RS-232
  • 500 МHz clock rate
  • 130 nm process
  • die size 100 mm2
  • ~45 million transistors
  • power consumption 5W

    • References

    MCST-R500S Wikipedia
    (Text) CC BY-SA


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