Goldmont is a microarchitecture for low-power Atom, Celeron and Pentium branded processors used in systems on a chip (SoCs) made by Intel. The Apollo Lake platform with 14 nm Goldmont core was unveiled at the Intel Developer Forum (IDF) in Shenzhen, China, April 2016. The Goldmont architecture borrows heavily from the Skylake Core processors, so offers more than 30 percent performance boost compare to the previous Braswell platform, and it can be used to implement power-efficient low-end devices including Cloudbooks, 2-in-1 netbooks, small PCs, IP cameras, and in-car entertainment systems.
Goldmont is the 2nd generation out-of-order low-power Atom microarchitecture designed for the entry level desktop and notebook computers. Goldmont is built on the 14 nm manufacturing process and supports up to four cores for the consumer devices. It includes the Intel Gen9 graphics architecture introduced with the Skylake.
The Goldmont microarchitecture builds on the success of the Silvermont microarchitecture, and provides the following enhancements:
An out-of-order execution engine with a 3-wide superscalar pipeline. Specifically:
The decoder can decode 3 instructions per cycle.
The microcode sequencer can send 3 µops per cycle for allocation into the reservation stations.
Retirement supports a peak rate of 3 per cycle.
Enhancement in branch prediction which de-couples the fetch pipeline from the instruction decoder.
Larger out-of-order execution window and buffers that enable deeper out-of-order execution across integer, FP/SIMD, and memory instruction types.
Fully out-of-order memory execution and disambiguation. The Goldmont microarchitecture can execute one load and one store per cycle (compared to one load or one store per cycle in the Silvermont microarchitecture). The memory execution pipeline also includes a second level TLB enhancement with 512 entries for 4KB pages.
Integer execution cluster in the Goldmont microarchitecture provides three pipelines and can execute up to three simple integer ALU operations per cycle.
SIMD integer and floating-point instructions execute in a 128-bit wide engine. Throughput and latency of many instructions have improved, including PSHUFB with 1-cycle throughput (versus 5 cycles for Silvermont microarchitecture) and many other SIMD instructions with doubled throughput.
Throughput and latency of instructions for accelerating encryption/description (AES) and carry-less multiplication (PCLMULQDQ) have been improved significantly in the Goldmont microarchitecture.
The Goldmont microarchitecture provides new instructions with hardware accelerated secure hashing algorithm, SHA1 and SHA256.
The Goldmont microarchitecture also adds support for the RDSEED instruction for random number generation meeting the NIST SP800-90C standard.
PAUSE instruction latency is optimized to enable better power efficiency.
A 14 nm manufacturing process
SoC (System on Chip) architecture
3D tri-gate transistors
Consumer chips up to quad-cores
Supports SSE4.2 instruction set
Supports Intel SHA extensions
Supports Intel MPX (Memory Protection Extensions)
Gen 9 Intel HD Graphics with DirectX 12, OpenGL 4.4 (Opengl 4.5 on Linux), OpenGL ES 3.2 and OpenCL 2.0 support.
HEVC Main10 & VP9 Profile0 hardware decoding support
10 W thermal design power (TDP) Desktop or Server processors
4.0 to 6.0 W TDP mobile processors
eMMC 5.0 technology to connect to NAND flash storage
USB 3.1 & USB Type-C specification
Support for DDR3L, LPDDR3, and LPDDR4 memory
List of desktop processors as follows:
List of mobile processors as follows:
List of embedded processors as follows:
Willow Trail platform was canceled. Apollo Lake will be offered instead.
