The FLAGS register is the status register in Intel x86 microprocessors that contains the current state of the processor. This register is 16 bits wide. Its successors, the EFLAGS and RFLAGS registers, are 32 bits and 64 bits wide, respectively. The wider registers retain compatibility with their smaller predecessors.
Contents
The fixed bits at bit positions 1, 3 and 5 and carry, parity, adjust, zero and sign flags are inherited from an even earlier architecture, 8080. The adjust flag used to be called auxiliary carry bit in 8080 and half-carry bit in the Zilog Z80 architecture.
USE
The POPF, POPFD, and POPFQ instructions read from the stack the first 16, 32, and 64 bits of the flags register, respectively. POPFD was introduced with the i386 architecture and POPFQ with the x64 architecture. In 64-bit mode, PUSHF/POPF and PUSHFQ/POPFQ are available but not PUSHFD/POPFD.
The following assembly code changes the direction flag (DF):
In practical software, the cld and std instructions are used to clear and set the direction flag, respectively. Some instructions in assembly language use the FLAGS register. The conditional jump instructions use certain flags to compute. For example, jz uses the zero flag, jc uses the carry flag and jo uses the overflow flag. Other conditional instructions look at combinations of several flags.
Determination of processor type
Testing if certain bits in the FLAGS register are changeable allows determining what kind of processor is installed. For example, the alignment flag can only be changed on the 486 and above, so if it can be changed then the CPU is a 486 or higher. These methods of processor detection were not made obsolete by the CPUID instruction introduced with the Intel Pentium, as CPUID is not implemented in these older CPUs.