The Atmel AVR instruction set is the machine language for the Atmel AVR, a modified Harvard architecture 8-bit RISC single chip microcontroller which was developed by Atmel in 1996. The AVR was one of the first microcontroller families to use on-chip flash memory for program storage.
Contents
Processor registers
There are 32 general-purpose 8-bit registers, R0–R31. All arithmetic and logic operations operate on those registers; only load and store instructions access RAM.
A limited number of instructions operate on 16-bit register pairs. The lower-numbered register of the pair holds the least significant bits and must be even-numbered. The last three register pairs are used as pointer registers for memory addressing. They are known as X (R27:R26), Y (R29:R28) and Z (R31:R30). Postincrement and predecrement addressing modes are supported on all three. Y and Z also support a six-bit positive displacement.
Instructions which allow an immediate value are limited to registers R16–R31 (8-bit operations) or to register pairs R25:R24–R31:R30 (16-bit operations ADIW and SBIW). Some variants of the MUL operation are limited to eight registers, R16 through R23.
Special purpose registers
In addition to these 32 general-purpose registers, the CPU has a few special-purpose registers:
Status bits
The status register bits are:
- C Carry flag. This is a borrow flag on subtracts.
- Z Zero flag. Set to 1 when an arithmetic result is zero.
- N Negative flag. Set to a copy of the most significant bit of an arithmetic result.
- V Overflow flag. Set in case of two's complement overflow.
- S Sign flag. Unique to AVR, this is always N⊕V, and shows the true sign of a comparison.
- H Half carry. This is an internal carry from additions and is used to support BCD arithmetic.
- T Bit copy. Special bit load and bit store instructions use this bit.
- I Interrupt flag. Set when interrupts are enabled.
Addressing
The following address spaces are available:
The first 64 I/O registers are accessible through both the I/O and the data address space. They have therefore two different addresses. These are usually written as "0x00 (0x20)" through "0x3F (0x5F)", where the first item is the I/O address and the second, in parentheses, the data address.
The special-purpose CPU registers, with the exception of PC, can be accessed as I/O registers. Some registers (RAMPX, RAMPY) may not be present on machines with less than 64 KiB of addressable memory.
A typical ATmega memory map may look like:
where RAMEND is the last RAM address. In parts lacking extended I/O the RAM would start at 0x0060.
Instruction timing
Arithmetic operations work on registers R0-R31 but not directly on RAM and take one clock cycle, except for multiplication and word-wide addition (ADIW and SBIW) which take two cycles.
RAM and I/O space can be accessed only by copying to or from registers. Indirect access (including optional postincrement, predecrement or constant displacement) is possible through registers X, Y, and Z. All accesses to RAM takes two clock cycles. Moving between registers and I/O is one cycle. Moving eight or sixteen bit data between registers or constant to register is also one cycle. Reading program memory (LPM) takes three cycles.
Instruction list
Instructions are one 16-bit word long, save for those including a 16-bit or 22-bit address, which take two words.
There are two types of conditional branches: jumps to address and skips. Conditional branches (BRxx) can test an ALU flag and jump to specified address. Skips (SBxx) test an arbitrary bit in a register or I/O and skip the next instruction if the test was true.
In the following:
Instruction set inheritance
Not all instructions are implemented in all Atmel AVR controllers. This is the case of the instructions performing multiplications, extended loads/jumps/calls, long jumps, and power control.
Instruction encoding
Bit assignments:
The Atmel AVR uses many split fields, where bits are not contiguous in the instruction word. The load/store with offset instructions are the most extreme example where a 6-bit offset is broken into three pieces.