Altera Hardware Description Language (AHDL) is a proprietary hardware description language (HDL) developed by Altera Corporation. AHDL is used for digital logic design entry for Altera's complex programmable logic devices (CPLDs) and field-programmable gate arrays (FPGAs). It is supported by Altera's MAX-PLUS and Quartus series of design software. AHDL has an Ada-like syntax and its feature set is comparable to the synthesizable portions of the Verilog and VHDL hardware description languages. In contrast to HDLs such as Verilog and VHDL, AHDL is a design-entry language only; all of its language constructs are synthesizable. By default, Altera software expects AHDL source files to have a .tdf extension (Text Design Files).
Example
% a simple AHDL up counter, released to public domain 13 November 2006 % % [block quotations achieved with percent sign] % % like c, ahdl functions must be prototyped % % PROTOTYPE: FUNCTION COUNTER (CLK) RETURNS (CNTOUT[7..0]); % % function declaration, where inputs, outputs, and bidirectional pins are declared % % also like c, square brackets indicate an array % SUBDESIGN COUNTER ( CLK :INPUT; CNTOUT[7..0] :OUTPUT; ) % variables can be anything from flip-flops (as in this case), tri-state buffers, state machines, to user defined functions % VARIABLE TIMER[7..0]: DFF; % as with all hardware description languages, think of this less as an algorithm and more as wiring nodes together % BEGIN DEFAULTS TIMER[].prn = VCC; % this takes care of d-ff resets % TIMER[].clrn = VCC; END DEFAULTS; TIMER[].d = TIMER[].q + H"1"; END;References
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