**AND-OR-Invert** (AOI) logic and AOI gates are two-level compound (or complex) logic functions constructed from the combination of one or more AND gates followed by a NOR gate. Construction of AOI cells is particularly efficient using CMOS technology where the total number of transistor gates can be compared to the same construction using NAND logic or NOR logic. The complement of AOI Logic is OR-AND-Invert (OAI) logic where the OR gates precede a NAND gate.

AOI gates perform one or more AND operations followed by an OR operation and then an inversion. For example, a 2-2 AOI gate can be represented by the boolean equation and truth table:

F
=
(
A
∧
B
)
∨
(
C
∧
D
)
¯

A 2-1 AOI gate can be represented by following the boolean equation and truth table:

F
=
A
∨
(
B
∧
C
)
¯

Larger AOI gates, such as 4-3 AOI or 3-3-3 AOI can also be used.

AOI and OAI gates can be readily implemented in CMOS circuitry. AOI gates are particularly advantaged in that the total number of transistors (or gates) is less than if the AND, NOT, and OR functions were implemented separately. This results in increased speed, reduced power, smaller area, and potentially lower fabrication cost. For example, a 2-1 AOI gate can be constructed with 6 transistors in CMOS compared to 10 transistors using a 2-input NAND gate (4 transistors), an inverter (2 transistors), and a 2-input NOR gate (4 transistors).

In NMOS logic, only the lower half of the CMOS circuit is used, in combination with a load device, or pull-up transistor (typically a depletion load or a dynamic load).

AOI gates are similarly efficient in transistor–transistor logic (TTL). The TTL 7400 line included a number of AOI gate parts, such as the 7451 dual 2-wide 2-input AND-OR-invert gate and the 7464 4-2-3-2-input AND-OR-invert gate.