Supriya Ghosh (Editor)

8250 UART

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8250 UART

The 8250 UART (universal asynchronous receiver/transmitter) is an integrated circuit designed for implementing the interface for serial communications. The part was originally manufactured by the National Semiconductor Corporation. It was commonly used in PCs and related equipment such as printers or modems. The 8250 included an on-chip programmable bit rate generator, allowing use for both common and special-purpose bit rates which could be accurately derived from an arbitrary crystal oscillator reference frequency.


The chip designations carry suffix letters for later versions of the same chip series. For example, the original 8250 was soon followed by the 8250A and 8250B versions that corrected some bugs. In particular, the original 8250 could repeat transmission of a character if the CTS line was asserted asynchronously during the first transmission attempt.

Due to the high demand, other manufacturers soon began offering compatible chips. Western Digital offered WD8250 chip under Async Communications Interface Adapter (ACIA) and Async Communications Element (ACE) names.

The 16450(A) UART, commonly used in IBM PC/AT-series computers, improved on the 8250 by permitting higher serial line speeds.

With the introduction of multitasking operating systems on PC hardware, such as OS/2, Windows NT or various flavours of UNIX, the short time available to serve character-by-character interrupt requests became a problem, therefore the IBM PS/2 serial ports introduced the 16550(A) UARTs that had a built-in 16 byte FIFO or buffer memory to collect incoming characters.

Later models added larger memories, supported higher speeds, combined multiple ports on one chip and finally became part of the now-common Super I/O circuits combining most input/output logic on a PC motherboard.


The line interface consists of: SOUT, SIN, /RTS, /DTR, DSR, /DCD, /CTS, /RI

Clock interface: XIN, XOUT, /BAUDOUT, RCLK

Computer interface: D0..D7, /RD, /WR, INTRPT, MR, A0,A1,A2, ADS, WR, RD, /CS2, CS1, CS0

The interrupt line will when the IER bit has enabled it be triggered to go high when one of the following events occur: Receiver line status, Received data available, Transmitter holding register empty, and MODEM status. The interrupt signal is reset to low level upon the appropriate interrupt service or a reset operation (via MR).


8250 UART was introduced with the IBM PC (1981). The 8250A and 8250B revisions were later released, and the 16450 was introduced with the IBM Personal Computer/AT (1984).

The main difference between releases was the maximum allowed communication speed.

A very similar, but slightly incompatible variant of this chip is the Intel 8251.


8250 UART Wikipedia