In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the 10 nanometer (10 nm) node as the technology node following the 14 nm node. "10 nm class" denotes chips made using process technologies between 10 and 20 nanometers.
As of 2016, 10 nm devices are still under commercial development. Commercial release is confirmed for 2017 by Samsung.
The ITRS's original naming of this technology node was "11 nm". According to the 2007 edition of the roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a DRAM should be 11 nm. Pat Gelsinger, at the time serving as Intel's Chief Technology Officer, claimed in 2008 that Intel saw a 'clear way' towards the 10 nm node. At the 11 nm node, Intel expected (in 2006) to be using a half-pitch of around 21 nm, in 2015, Nvidia's chief scientist, William Dally, claimed (in 2009) that they would also reach 11 nm semiconductors in 2015, a transition he claimed would be facilitated principally through new electronic design automation tools.
As of 2014, "10 nm" node is projected to be a metal pitch of 40–50 nm.
This 10 nm design rule is considered likely to be realized by multiple patterning, given the difficulty of implementing EUV lithography.
While the roadmap has been based on the continuing extension of CMOS technology, even this roadmap does not guarantee that silicon-based CMOS will extend that far. This is to be expected, since the gate length for this node may be smaller than 6 nm, and the corresponding gate dielectric thickness would scale down to a monolayer or even less. Scientists have estimated that transistors at these dimensions are significantly affected by quantum tunnelling. As a result, non-silicon extensions of CMOS, using III-V materials or Carbon nanotube/nanowires, as well as non-CMOS platforms, including molecular electronics, spin-based computing, and single-electron devices, have been proposed. Hence, this node marks the practical beginning of nanoelectronics.
The extensive use of ultra-low-k dielectrics (such as spin-on polymers or other porous materials) means that conventional photolithography, etch, or even chemical-mechanical polishing processes are unlikely to be used, because these materials contain a high density of voids and gaps. At the ~10 nm scale, quantum tunneling (especially through gaps) becomes a significant phenomenon. Controlling gaps on these scales by means of electromigration can produce interesting electrical properties.
Quantum tunneling may be advantageous if its effect on device behavior can be understood, and exploited, in the design. Future transistors may have insulating channels. An electron wave function decays exponentially in a "classically forbidden" region at a rate that can be controlled by the gate voltage. Interference effects are also possible; Alternate option is in heavier mass semiconducting channels. Photoemission electron microscopy (PEEM) data has been used to show that low energy electrons ~1.35 eV could travel as far as ~15 nm in SiO2, despite an average measured attenuation length of 1.18 nm.
Technology demos and pre-production.
In April 2015, TSMC announced that 10 nm production would begin at the end of 2016.
On 23 May 2015, Samsung Electronics showed off a 300 mm wafer of 10 nm FinFET chips.
In c. Aug 2016 Intel began trial production at 10 nm.
On 17 Oct 2016 Samsung Electronics announced mass production at 10 nm.
As of mid 2016 Semiconductor business Intel, and foundries at TSMC, and Samsung were all expected to ship or begin volume production of 10 nm devices in the first quarter of 2017, with foundry customers for 2017 including Qualcomm (Snapdragon 835) at Samsung, and Apple Inc and MediaTek at TSMC.