Rahul Sharma (Editor)

TILE Gx

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Produced
  
2010

Common manufacturer(s)
  
TSMC

Min. feature size
  
40nm to 40nm

Designed by
  
Tilera

Max. CPU clock rate
  
1000 MHz to 1500 MHz

Microarchitecture
  
VLIW RISC

TILE-Gx is a multicore processor family by Tilera. It consists of a mesh network of up to 100 cores. It is to be produced by TSMC with 40 nm. It was announced on February 19, 2013 that Tilera would produce a 72-core Tile-Gx CPU capable of processing high-bandwidth networks.

  • 64-bit core (3-issue)
  • 32 KB L1 I-cache, 32 KB L1 D-cache (per core)
  • 256 KB L2 cache (per core)
  • up to 26 MB L3 cache (per chip)
  • 4 MAC/cycle with SIMD extensions
  • 2 or 4 ECC 72-bit DDR3 memory controllers (up to 2.1 GHz)
  • Built-in crypto accelerator with 40 Gbit/s encryption (small packet) and 20 Gbit/s full-duplex compression, true random number generator, RSA accelerator

    • References

    TILE-Gx Wikipedia
    (Text) CC BY-SA