Rahul Sharma (Editor)

Puma (microarchitecture)

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Common manufacturer(s)
  
AMD

Min. feature size
  
28 nm

Cores
  
2–4

Max. CPU clock rate
  
1.35 GHz to 2.5 GHz

Instruction set
  
AMD64 (x86-64)

Produced
  
From mid-2014 to present

The Puma Family 16h is a low-power microarchitecture by AMD for its APUs. It succeeds the Jaguar as a second-generation version, targets the same market, and belongs to the same AMD architecture Family 16h. The Beema line of processors are aimed at low-power notebooks, and Mullins are targeting the tablet sector.

Contents

Design

The Puma cores use the same microarchitecture as Jaguar, and inherits the design:

  • Out-of-order execution and Speculative execution, up to 4 CPU cores
  • Two-way integer execution
  • Two-way 128-bit wide floating-point and packed integer execution
  • Integer hardware divider
  • Puma does not feature clustered multi-thread (CMT), meaning that there are no "modules"
  • Puma does not feature Heterogeneous System Architecture or zero-copy
  • 32 KiB instruction + 32 KiB data L1 cache per core
  • 1–2 MiB unified L2 cache shared by two or four cores
  • Integrated single channel memory controller supporting 64bit DDR3L
  • 3.1 mm2 area per core

    • Instruction set support

    Like Jaguar, the Puma core has support for the following instruction sets and instructions: MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, BMI1, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM (POPCNT/LZCNT), and AMD-V.

    Improvements over Jaguar

  • 19% CPU core leakage reduction at 1.2V
  • 38% GPU leakage reduction
  • 500 mW reduction in memory controller power
  • 200 mW reduction in display interface power
  • Chassis temperature aware turbo boost
  • Selective boosting according to application needs (intelligent boost)
  • Support for ARM TrustZone via integrated Cortex-A5 processor
  • Support for DDR3L-1866 memory

    • Puma+

    AMD released a revision of Puma core, Puma+, as a part of the Carrizo-L platform in 2015. The differences in the CPU microarchitecture are unclear. Puma+ featured 2 or 4 cores up to 2.5GHz and required the newer FP4 socket.

    References

    Puma (microarchitecture) Wikipedia
    (Text) CC BY-SA