Created H1 2018 Architecture x86 | Transistors 10 nm transistors Socket BGA
LGA 1151 | |
Instructions MMX, AES-NI, CLMUL, FMA3 Extensions x86-64, Intel 64
SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2
AVX, AVX2, AVX-512, SHA, TXT, TSX, SGX
VT-x, VT-d | ||
Cannon Lake (formerly Skymont) is Intel's codename for the 10-nanometer die shrink of the Kaby Lake microarchitecture, expected to be released late in the first half of 2018. As a die shrink, Cannon Lake is a new process in Intel's "Process-Architecture-Optimization" execution plan as the next step in semiconductor fabrication. Cannon Lake will be used in conjunction with Intel 300 Series chipsets.
It has been speculated for a long time that reaching smaller process nodes would become impractical, leading to the end of Moore's Law. Intel however believes that it will be possible to reach at least 7 nm, though it will perhaps require use of materials other than silicon, such as indium gallium arsenide (InGaAs).
Due to low 10 nm yields, Cannon Lake will be limited to 15 Watt U and 5 Watt Y-series system-on-chip parts with GT2. Higher-power mobile and desktop platforms will receive an update in the form of a second 14 nm process refinement with Coffee Lake, which is said to share Cannon Lake's architectural refinements.
Intel demonstrated a laptop with an unknown Cannon Lake CPU at CES 2017. The company expects Cannon Lake based products to be available at the end of 2017.
The successors of the Cannon Lake microarchitecture will be Icelake (2019) and Tigerlake (2020), which will represent Architecture and Optimization of the Intel Process-Architecture-Optimization Model.